US-12622233-B2 - Method of fabricating semiconductor device

Abstract

A method of fabricating a semiconductor device, includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming mandrel lines on the hard mask layer, each of the mandrel lines extending in a first direction; forming spacers on both sidewalls of each of mandrel lines; removing the plurality of mandrel lines from the spacers; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer; forming a second linear opening corresponding to a second region of the space between the adjacent ones, the second linear opening being adjacent to the first linear opening in the first direction; forming trenches in the dielectric layer using the hard mask layer; and interconnection lines by filling the trenches with a conductive material.

Inventors

• Seowoo Nam
• Kyungsoo Kim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230807

Priority Date

20220819

Claims (20)

1. 1 . A method of fabricating a semiconductor device, comprising: forming a hard mask layer on a target layer; forming a plurality of mandrel lines on the hard mask layer, wherein the plurality of mandrel lines extend in a first direction and are arranged in a second direction that intersects the first direction; forming spacers on sidewalls of each of the plurality of mandrel lines; removing the plurality of mandrel lines from the spacers, wherein the spacers are arranged at intervals defined by a design width of a target pattern; forming a first photomask having a first opening on the hard mask layer on which the spacers are formed, wherein the first opening exposes a first linear space defined as a first region of a first space between adjacent ones of the spacers; forming a first linear opening corresponding to the first linear space in the hard mask layer by etching the hard mask layer using the first photomask; forming a second photomask having a second opening on the hard mask layer on which the spacers are formed, after removing the first photomask, wherein the second opening exposes a second linear space defined as a second region of the first space between the adjacent ones of the spacers; forming a second linear opening corresponding to the second linear space in the hard mask layer by etching the hard mask layer using the second photomask; and etching the target layer using the hard mask layer, after removing the second photomask, wherein at least one of the first opening and the second opening exposes portions of the adjacent spacers, and the exposed portions of the adjacent spacers function as a mask in the forming the first linear opening and the second linear opening.
2. 2 . The method of claim 1 , wherein a distance between the first linear space and the second linear space in the first direction is 20 nm or less.
3. 3 . The method of claim 1 , wherein at least one of the first photomask and the second photomask has at least one additional opening for exposing an additional linear space, and the forming the first linear opening and/or the second linear opening includes forming at least one additional linear opening through the at least one additional opening in the hard mask layer.
4. 4 . The method of claim 3 , wherein the at least one additional linear space is defined by at least one region of a space between adjacent ones of the spacers.
5. 5 . The method of claim 3 , wherein the at least one additional linear space is defined by a third region of a second space between other adjacent ones of the spacers.
6. 6 . The method of claim 1 , further comprising: forming a third photomask having a third opening on the hard mask layer on which the spacers are formed, wherein the third opening has a width greater than a width of each of the first and second linear openings in the second direction, and exposes at least one spacer of the spacers; removing an exposed portion of the at least one spacer using the third photomask; and etching the hard mask layer using the third photomask, to form a wide opening having a width greater than the design width, in the hard mask layer.
7. 7 . The method of claim 6 , wherein the removing the exposed portion of the at least one spacer and the etching the hard mask layer are performed by a same etching process.
8. 8 . The method of claim 6 , wherein sides of the wide opening opposing in the first direction are curved.
9. 9 . The method of claim 6 , wherein the wide opening has a width extending over the at least one spacer and two spaces adjacent thereto in the second direction.
10. 10 . The method of claim 1 , wherein the forming the plurality of mandrel lines comprises forming a mandrel pattern having a second width greater than a first width of each of the plurality of mandrel lines, the forming the spacers on both sidewalls of each of the plurality of mandrel lines comprises forming a perimeter spacer along sidewalls of the mandrel pattern to surround the mandrel pattern, and the removing the plurality of mandrel lines comprises removing the mandrel pattern from the perimeter spacer.
11. 11 . The method of claim 10 , further comprising: forming a third photomask having a third opening on the hard mask layer in which the spacers are formed, wherein the third opening exposes a portion of the hard mask layer surrounded by the perimeter spacer; and etching the hard mask layer using the third photomask, to form a wide opening having the second width in the hard mask layer.
12. 12 . The method of claim 10 , wherein one of the first photomask or the second photomask comprises a third opening exposing a portion of the hard mask layer surrounded by the perimeter spacer, and either or both of the forming the first linear opening or the forming the second linear opening comprises forming a wide opening having the second width in the hard mask layer.
13. 13 . The method of claim 1 , wherein the forming the spacers comprises: conformally forming a spacer material layer on the plurality of mandrel lines and the hard mask layer, and performing anisotropic etching on the spacer material layer.
14. 14 . The method of claim 1 , wherein the forming a second photomask includes forming the second photomask on the spacers.
15. 15 . The method of claim 1 , wherein the forming a second photomask includes forming the second photomask before removing the spacers.
16. 16 . A method of fabricating a semiconductor device, comprising: forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming a plurality of mandrel lines on the hard mask layer, wherein the plurality of mandrel lines extend in a first direction, and are arranged in a second direction, intersecting the first direction; forming spacers on both sidewalls of each of the plurality of mandrel lines; removing the plurality of mandrel lines from the spacers, wherein the spacers are arranged at intervals defined by a design width of a target pattern; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers in the hard mask layer using a first photomask; forming a second linear opening corresponding to a second region of the space between the adjacent ones of the spacers in the hard mask layer using a second photomask, wherein the second linear opening is adjacent to the first linear opening in the first direction; forming first and second trenches respectively corresponding to the first and second linear openings in the dielectric layer using the hard mask layer; forming a plurality of interconnection lines by filling the first and second trenches with a conductive material; and forming a wide opening having a width greater than a width of each of the first and second linear openings, in the hard mask layer using a third photomask, wherein the wide opening is configured to expose at least one spacer of the spacers, wherein the forming the wide opening includes removing an exposed region of the at least one spacer using the third photomask.
17. 17 . The method of claim 16 , wherein each of sides of the wide opening opposing in the first direction has non-straight line.
18. 18 . The method of claim 16 , wherein the forming the first linear opening and/or the forming the second linear opening comprises forming at least one additional linear opening in the hard mask layer.
19. 19 . A method of fabricating a semiconductor device, comprising: forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming a plurality of mandrel lines and at least one mandrel pattern on the hard mask layer, wherein each of the plurality of mandrel lines extend in a first direction, respectively, and the plurality of mandrel lines are arranged in a second direction, intersecting the first direction, wherein the at least one mandrel pattern has a width, greater than a width of each of the plurality of mandrel lines; forming first spacers and a second spacer on both sidewalls of each of the plurality of mandrel lines and sidewalls surrounding the at least one mandrel pattern, respectively; removing the plurality of mandrel lines and the at least one mandrel pattern from the first spacers and the second spacer, wherein a distance between the first spacers defines a design width of a target pattern; forming a first linear opening corresponding to a first region of a first space between adjacent ones of the first spacers in the hard mask layer using a first photomask; forming a second linear opening corresponding to a second region of the first space between the adjacent ones of the first spacers in the hard mask layer using a second photomask, wherein the second linear opening is adjacent to the first linear opening in the first direction; forming a wide opening corresponding to a second space surrounded by the second spacer in the hard mask layer; forming first and second trenches respectively corresponding to the first and second linear openings and the wide opening in the dielectric layer using the hard mask layer; and forming a plurality of interconnection lines by filling the first and second trenches with a conductive material.
20. 20 . The method of claim 19 , wherein the forming the wide opening is performed simultaneously with the forming the first linear opening or the forming the second linear opening.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims benefit of priority to Korean Patent Application No. 10-2022-0104121 filed on Aug. 19, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND Various example embodiments relate to a method of fabricating a semiconductor device. Various types of self-aligned patterning such as double or quadruple patterning have been extensively developed/researched as a method of realizing a high resolution of a fine pattern in a semiconductor process. A self-aligned patterning process may be used, for example, in an interconnection line process such as a back-end-of-line (BEOL) and a fine pattern forming process. According to a recent demand for spacing reduction, defects in the conventional cut-off process introduced for line separation in the self-aligned patterning process may occur, which may cause an undesirable short circuit between interconnection lines in subsequent processes. SUMMARY Various example embodiments provide a method of fabricating a semiconductor device by reducing an interval between metal patterns. According to some example embodiments, a method of fabricating a semiconductor device includes forming a hard mask layer on a target layer; forming a plurality of mandrel lines on the hard mask layer, wherein the plurality of mandrel lines extend in a first direction, and are arranged in a second direction that intersects the first direction; forming spacers on both sidewalls of the plurality of mandrel lines; removing the plurality of mandrel lines from the spacers, wherein the spacers are arranged at intervals defined by a design width of a target pattern; forming a first photomask, having a first opening, on the hard mask layer in which the spacers are formed, wherein the first opening exposes a first linear space defined as a first region of a first space between adjacent ones of the spacers; forming a first linear opening corresponding to the first linear space in the hard mask layer by etching the hard mask layer using the first photomask; forming a second photomask having a second opening on the hard mask layer in which the spacers are formed, after removing the first photomask, wherein the second opening exposes a second linear space defined as a second region of the first space between the adjacent ones of the spacers; forming a second linear opening corresponding to the second linear space in the hard mask layer by etching the hard mask layer using the second photomask; and etching the target layer using the hard mask layer, after removing the second photomask. According to various example embodiments, a method of fabricating a semiconductor device includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming a plurality of mandrel lines on the hard mask layer, wherein the plurality of mandrel lines extend in a first direction, respectively, and are arranged in a second direction, intersecting the first direction; forming spacers on both sidewalls of the plurality of mandrel lines; removing the plurality of mandrel lines from the spacers, wherein the spacers are arranged at intervals defined by a design width of a target pattern; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer using a first photomask; forming a second linear opening corresponding to a second region of the space between the adjacent ones of the spacers in the hard mask layer using a second photomask, wherein the second linear opening is adjacent to the first linear opening in the first direction; forming first and second trenches respectively corresponding to the first and second linear openings in the dielectric layer using the hard mask layer; and forming a plurality of interconnection lines by filling the first and second trenches with a conductive material. According to some example embodiments, a method of fabricating a semiconductor device includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming a plurality of mandrel lines and at least one mandrel pattern on the hard mask layer, wherein the plurality of mandrel lines extend in a first direction, respectively, and are arranged in a second direction, intersecting the first direction, wherein the at least one mandrel pattern has a width, greater than a width of each of the plurality of mandrel lines; forming first spacers and a second spacer on both sidewalls of the plurality of mandrel lines and sidewalls surrounding the at least one mandrel pattern, respectively; removing the plurality of mandrel lines and the at least one mandrel pattern from the first spacers and the second spacer, wherein a distance between the first spacers defines a design width of a target pattern; forming a first linear opening corresponding to a first region of a first s