US-12622235-B2 - Method of manufacturing semiconductor device

US12622235B2US 12622235 B2US12622235 B2US 12622235B2US-12622235-B2

Abstract

A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Inventors

Chih-Min HSIAO
Chien-Wen Lai
Shih-Chun Huang
Yung-Sung Yen
Chih-Ming Lai
Ru-Gun Liu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20240510

Claims (20)

1 . A method of manufacturing a semiconductor device, the method comprising: forming an opening in a first layer to expose a second layer underlying the first layer; converting a first portion of the first layer to a mask by modifying an etch rate characteristic of the first portion of the first layer proximal to the opening; directionally etching to remove a second portion of the first layer without removing the first portion of the first layer converted to the mask to further expose the second layer; and etching the second layer using the mask as an etching mask.
2 . The method of claim 1 , wherein modifying the etch rate characteristic of the first portion of the first layer includes implanting the first portion of the first layer with one or more etch rate modifying species.
3 . The method of claim 2 , wherein the one or more etch rate modifying species are selected from nitrogen, oxygen, fluorine, arsenic, boron, carbon, phosphorus, gallium, indium, aluminum, antimony, and germanium.
4 . The method of claim 2 , wherein implanting the first portion of the first layer with the one or more etch rate modifying species increases an etch resistance of the first portion of the first layer by at least a factor of two when compared to an etch resistance of an un-implanted portion of the first layer that is not implanted with the one or more etch rate modifying species.
5 . The method of claim 1 , wherein the first layer includes a semiconductor material.
6 . The method of claim 5 , wherein the second layer includes a dielectric material.
7 . A method of manufacturing a semiconductor device, the method comprising: forming an opening in a first layer to expose a second layer underlying the first layer; forming a mask by modifying an etch rate characteristic of a first portion of the first layer proximal to the opening; directionally etching to remove a second portion of the first layer without removing the mask to further expose the second layer; forming a spacer layer over a third portion of the first layer, the mask, and the exposed second layer; forming a first pattern through the spacer layer to expose the second layer; forming a second pattern by removing the first layer to further expose the second layer; and etching using the mask and the spacer layer to extend the second pattern and expose an underlying substrate.
8 . The method of claim 7 , wherein a first portion of the second layer remains under the mask after exposing the underlying substrate.
9 . The method of claim 8 , wherein a second portion of the second layer remains under the spacer layer after etching to expose the underlying substrate.
10 . The method of claim 7 , wherein forming the opening in the first layer includes performing a lithographic process comprising depositing a pattern transfer layer on the first layer, forming a pattern in the pattern transfer layer, and etching the first layer through the pattern.
11 . The method of claim 7 , wherein modifying the etch rate characteristic of the first portion of the first layer includes implanting the first portion of the first layer with one or more etch rate modifying species.
12 . The method of claim 11 , wherein implanting the first portion of the first layer with the one or more etch rate modifying species increases an etch resistance of the first portion of the first layer by at least a factor of two when compared to an etch resistance of an un-implanted portion of the first layer that is not implanted with the one or more etch rate modifying species.
13 . The method of claim 7 , wherein the spacer layer is conformally formed over a sidewall and a top of the third portion of the first layer, over a sidewall and a top of the mask, and over the exposed second layer.
14 . A method of manufacturing a semiconductor device, the method comprising: providing a layered structure comprising a first layer, a substrate, and a second layer between the first layer and the substrate; forming an opening in the first layer to expose the second layer; forming a mask by modifying an etch rate characteristic of a first portion of the first layer proximal to the opening; directionally etching to remove a second portion of the first layer without removing the mask to further expose the second layer; forming a spacer layer over the second layer and a sidewall of a third portion of the first layer; patterning a hole through the spacer layer to expose the second layer; removing the first layer; and patterning the second layer using the mask and the spacer layer as etching masks.
15 . The method of claim 14 , wherein modifying the etch rate characteristic of the first portion of the first layer includes implanting the first portion of the first layer with one or more etch rate modifying species.
16 . The method of claim 15 , wherein implanting the first portion of the first layer with the one or more etch rate modifying species increases an etch resistance of the first portion of the first layer by at least a factor of two when compared to an etch resistance of an un-implanted portion of the first layer that is not implanted with the one or more etch rate modifying species.
17 . The method of claim 14 , further comprising removing a portion of the spacer layer from sidewalls of the mask before patterning the second layer.
18 . The method of claim 14 , wherein the first layer includes a semiconductor material.
19 . The method of claim 18 , wherein the second layer includes a dielectric material.
20 . The method of claim 14 , wherein patterning the second layer extends the hole to expose the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a Continuation of U.S. patent application Ser. No. 18/123,820 filed on Mar. 20, 2023, which is a Continuation of U.S. patent application Ser. No. 17/240,692 filed on Apr. 26, 2021, now U.S. Pat. No. 11,610,778, which is a Continuation of U.S. patent application Ser. No. 16/503,277 filed on Jul. 3, 2019, now U.S. Pat. No. 10,991,583, which claims priority to U.S. Provisional Applications No. 62/738,456 filed on Sep. 28, 2018, the entire disclosure of each of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to a process of fabricating an integrated circuit, and more specifically to a self-aligned litho-etch (SALE) process. BACKGROUND As the size of semiconductor devices becomes smaller than the wavelength of illumination used in photolithography tools, techniques such as double patterning are used to obtain patterns for printing critical design layers. However, some double patterning techniques such as litho-etch, litho-etch (LELE) suffer from potential degradation due to misalignment or overlay issues. Techniques such as self-aligned double patterning (SADP) have been developed to avoid problems such as misalignment and overlay errors. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a flow chart of a method of performing a self-aligned litho-etch patterning in accordance with an embodiment of the present disclosure. FIGS. 2A, 3A, 4A, 5A, 6A, 7A and 8A are schematic top views of a substrate corresponding to various acts of the method of performing a SALE process in accordance with some embodiments of the present disclosure. FIGS. 2B, 3B, 4B, 5B, 6B, 7B and 8B are corresponding schematic cross-section views of a substrate corresponding to various acts of the method of performing SALE process in accordance with some embodiments of the present disclosure. FIGS. 2C and 5C are schematic cross-section views of a substrate corresponding respectively to an operation of forming a first plurality of openings in a first layer of a hard mask and a second plurality of openings in a spacer layer disposed on the first layer. FIG. 9 illustrates a flow chart of a method of performing a self-aligned litho-etch patterning in accordance with another embodiment of the present disclosure. FIG. 10 illustrates an embodiment of a mask generation tool configured to generate a reusable cut mask. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus/device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. While methods disclosed herein are illustrated and described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example,