US-12622236-B2 - Support for a semiconductor structure

US12622236B2US 12622236 B2US12622236 B2US 12622236B2US-12622236-B2

Abstract

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

Inventors

Patrick Reynaud
Marcel Broekaart
Frédéric Allibert
Christelle Veytizou
Luciana Capello
Isabelle Bertrand

Assignees

SOITEC

Dates

Publication Date: 20260505
Application Date: 20220602
Priority Date: 20170126

Claims (20)

1 . A support for a semiconductor structure, comprising: a base substrate comprising one or more of silicon carbide and monocrystalline silicon; a silicon dioxide insulating layer on the base substrate, the silicon dioxide insulating layer having a thickness between 100 nm and 200 nm; a charge trapping layer on the silicon dioxide insulating layer, the charge trapping layer having a total thickness greater than 5 microns; an insulating layer on the charge trapping layer, wherein the insulating layer is silicon oxide or silicon nitride; a donor substrate on the insulating layer, wherein the donor substrate is silicon oxide or silicon nitride; and a useful layer over the insulating layer, the useful layer being formed from the donor substrate.
2 . The support for the semiconductor structure of claim 1 , wherein the base substrate comprises Czochralski (CZ) silicon containing interstitial oxygen.
3 . The support for the semiconductor structure of claim 1 , wherein the charge trapping layer comprises an alternating stack of at least one layer of charge trapping material and at least one intermediate layer.
4 . The support for the semiconductor structure of claim 3 , wherein the at least one intermediate layer comprises one or more of carbon, silicon oxide, and silicon nitride.
5 . The support for the semiconductor structure of claim 3 , wherein the at least one layer of charge trapping material has a thickness of 1 micron or less.
6 . A semiconductor structure, comprising: a silicon dioxide insulating layer on a base substrate, the silicon dioxide insulating layer having a thickness greater than 20 nm; a charge trapping layer on the silicon dioxide insulating layer, the charge trapping layer having a thickness greater than 5 microns; an insulating layer on the charge trapping layer, wherein the insulating layer is silicon oxide or silicon nitride; a donor substrate on the insulating layer, wherein the donor substrate is silicon oxide or silicon nitride; and a useful layer over the charge trapping layer and the insulating layer, the useful layer being formed from the donor substrate.
7 . The semiconductor structure of claim 6 , wherein the useful layer comprises a piezoelectric material.
8 . The semiconductor structure of claim 7 , wherein the piezoelectric material is lithium tantalate.
9 . A method of forming a support for a semiconductor structure, the method comprising: forming a silicon dioxide insulating layer on a base substrate, the silicon dioxide insulating layer having a thickness between 100 nm and 200 nm; depositing a charge trapping layer on the silicon dioxide insulating layer, the charge trapping layer having a total thickness greater than 5 microns; depositing an insulating layer on the charge trapping layer, wherein the insulating layer is silicon oxide or silicon nitride; depositing a donor substrate on the insulating layer, wherein the insulating layer is silicon oxide or silicon nitride; and forming a useful layer from the donor substrate.
10 . The method of claim 9 , wherein the base substrate comprises silicon and forming the silicon dioxide insulating layer on the base substrate comprises oxidizing an upper portion of the base substrate.
11 . The method of claim 9 , wherein the charge trapping layer has a resistivity higher than 1000 ohm·cm.
12 . The method of claim 9 , wherein depositing a charge trapping layer on the silicon dioxide insulating layer comprises depositing the charge trapping layer by one or more of a plasma-enhanced chemical vapor deposition (PECVD) process, a remote plasma-enhanced chemical vapor deposition (RPCVD) process, and a low-pressure chemical vapor deposition (LPCVD) process.
13 . The method of claim 9 , wherein forming the charge trapping layer on the first silicon dioxide insulating layer comprises forming at least one intermediate layer within the charge trapping layer, such that the charge trapping layer comprises alternating layers of a charge trapping material and the at least one intermediate layer.
14 . The method of claim 9 , wherein the base substrate comprises one or more of silicon, sapphire, glass, quartz, and silicon carbide.
15 . The method of claim 9 , wherein the charge trapping layer is rich in carbon or nitrogen.
16 . A method of forming a semiconductor structure, the method comprising: forming a silicon dioxide insulating layer on a base substrate, the silicon dioxide insulating layer having a thickness greater than 20 nm; forming a charge trapping layer on the silicon dioxide insulating layer to form a support structure, the charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns; forming an insulating layer on the charge trapping layer, wherein the insulating layer is silicon dioxide or silicon nitride; bonding a donor substrate to the support structure over the charge trapping layer and the insulating layer, wherein the donor substrate is silicon dioxide or silicon nitride; and thinning the donor substrate to form a useful layer on the support structure.
17 . The method of claim 16 , further comprising, before bonding a donor substrate to the support structure, forming an insulating layer on the charge trapping layer.
18 . The method of claim 17 , wherein forming an insulating layer on the charge trapping layer comprises one of oxidizing an upper portion of the charge trapping layer to form the insulating layer or depositing the insulating layer on the charge trapping layer.
19 . The method of claim 16 , wherein the donor substrate comprises an insulating layer on a surface thereof and the donor substrate is bonded to the support structure along a surface of the insulating layer.
20 . The method of claim 16 , wherein thinning the donor substrate to form a useful layer on the support structure comprises: forming a fragile zone in the donor substrate to delineate the useful layer; and detaching the donor substrate along the fragile zone to obtain the useful layer detached from the donor substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 16/476,415, filed Jul. 8, 2019, now U.S. Pat. No. 11,373,856, issued Jun. 28, 2022, which is a national phase entry under 35 U.S.C. § 371 of International Patent Application PCT/EP2018/050677, filed Jan. 11, 2018, designating the United States of America and published in English as International Patent Publication WO 2018/137937 A1 on Aug. 2, 2018, which claims the benefit under Article 8 of the Patent Cooperation Treaty to French Patent Application Serial No. 1750646, filed Jan. 26, 2017, the disclosure of each of which is hereby incorporated herein in its entirety by this reference. TECHNICAL FIELD The present disclosure relates to a support for a semiconductor structure. BACKGROUND Integrated devices are usually formed on substrates that mainly serve to hold them during their fabrication. However, the increase in the degree of integration and the expected performance of these devices has led to an increasingly tighter coupling of their performance and the properties of the substrate on which they are formed. This is particularly the case for RF devices processing signals the frequency of which is between about 3 kHz and 300 GHz, which are, in particular, employed in the telecommunications field (telephony, Wi-Fi, BLUETOOTH®, etc.). By way of example of device/substrate coupling, the electromagnetic fields generated by high-frequency signals propagating through the integrated devices penetrate into the bulk of the substrate and interact with any charge carriers found there. This leads to coupling losses that consume some of the power of the signal, and possibly to crosstalk between components. According to a second example of coupling, substrate charge carriers may generate undesired harmonics, which may interfere with the signals propagating through the integrated devices and degrade device quality. These effects are especially observable when the substrate employed comprises a buried insulating layer between a support and a useful layer on and in which the integrated devices are formed. Charges trapped in the insulating layer cause charges of complementary sign to accumulate under this insulating layer, forming a conductive plane in the support. In this conductive plane, mobile charges are liable to interact strongly with the electromagnetic fields generated by the components of the useful layer. To prevent or limit this effect, it is known to insert, between the buried insulating layer and the support, directly under the insulating layer, a charge trapping layer, for example, a layer of 1 to 5 microns of polycrystalline silicon. The boundaries of the grains forming the polycrystalline material then form charge traps, the trapped charge carriers possibly originating from the trapping layer itself or from the subjacent support. Thus, the formation of the conductive plane under the insulating layer is prevented. The fabrication of this type of substrate is, for example, described in documents FR2860341, FR2933233, FR2953640, US2015115480, U.S. Pat. Nos. 7,268,060 and 6,544,656. In the presence of a trapping layer, the device/substrate coupling remains dependent on the strength of the interaction between the electromagnetic fields and the mobile charges in the support, and hence on the depth of penetration of these fields into this support. The density and/or mobility of these charges depends on the resistivity of the support. When the resistivity of the support is relatively high (and therefore charge density relatively low), higher than 1000 ohm·cm, a trapping layer of 1 to 5 microns in thickness may be suitable for limiting device/substrate coupling, even when the electromagnetic field penetrates deeply into the support. The integrity of the signals, and hence the radiofrequency (RF) performance of the devices integrated into the useful layer, is thus preserved. In contrast, when the resistivity of the support is lower, lower than 1000 ohm·cm, or when the performance expected from the integrated device is high, it would be desirable to be able to form a very thick trapping layer, of greater than 5 microns, or even than 10 or 20 microns, in thickness, in order to shift the zone in which the charges are mobile deeper into the substrate and to limit the depth of penetration of the electromagnetic fields into this support. Interactions with these electromagnetic fields could thus be prevented and the performance of devices integrated into the useful layer improved. However, it has been observed that increasing the thickness of a trapping layer beyond 5 microns does not always lead to the expected improvement in performance, in particular, because this layer may recrystallize during heat treatments to which it is subjected. These heat treatments may correspond to those required to produce the substrate itself or to those required to fabricate an RF integrated device in or on the useful layer of the