US-12622237-B2 - Trench isolation connectors for stacked structures

US12622237B2US 12622237 B2US12622237 B2US 12622237B2US-12622237-B2

Abstract

Trench isolation connectors are disclosed herein for stacked semiconductor structures, and particularly, for stacked semiconductor structures having high voltage devices. An exemplary stacked device arrangement includes a first device substrate having a first device and a second device substrate having a second device. An isolation structure disposed in the second device substrate surrounds the second device. The isolation structure extends through the second device substrate from a first surface of the second device substrate to a second surface of the second device substrate. A conductive connector is disposed in the isolation structure. The conductive connector is connected to the second device and the first device. The conductive connector extends from the first surface of the second device substrate to the second surface of the second device substrate. The first device and the second device may be a first high voltage device and a second high voltage device, respectively.

Inventors

Wan-Jyun Syue
Hsueh-Liang Chou

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20230112

Claims (20)

1 . A stacked device arrangement comprising: a first device substrate having a first device; a second device substrate having a first surface opposite a second surface, wherein the second device substrate has a second device at the first surface of the second device substrate, an isolation structure disposed in the second device substrate, wherein the isolation structure and the second device substrate have a same thickness, such that the isolation structure extends through the second device substrate from the first surface of the second device substrate to the second surface of the second device substrate, and further wherein, in a top view, the isolation structure surrounds the second device; and a conductive connector disposed in the isolation structure, wherein the conductive connector is connected to the second device, the conductive connector is connected to the first device, and the conductive connector extends from the first surface of the second device substrate to the second surface of the second device substrate.
2 . The stacked device arrangement of claim 1 , wherein the first device is a first high voltage device and the second device is a second high voltage device.
3 . The stacked device arrangement of claim 1 , further comprising: a first chip that includes the first device substrate, wherein the first chip further includes a first multilayer interconnect (MLI) disposed over the first device substrate, wherein the first MLI is connected to the first device; and a second chip that includes the second device substrate, wherein the second chip further includes a second MLI disposed over the second device substrate, wherein the second MLI is connected to the second device.
4 . The stacked device arrangement of claim 3 , wherein: the first MLI provides a frontside of the first chip and the first device substrate provides a backside of the first chip; the second MLI provides a frontside of the second chip and the second surface of the second device substrate provides a backside of the second chip; and the backside of the second chip is attached to the frontside of the first chip and the conductive connector is connected to the first MLI and the second MLI.
5 . The stacked device arrangement of claim 3 , wherein: the first MLI provides a frontside of the first chip and the first device substrate provides a backside of the first chip; the second MLI provides a frontside of the second chip and the second surface of the second device substrate provides a backside of the second chip; and the backside of the second chip is attached to the frontside of the first chip by a bonding layer, an interconnect structure of the bonding layer is connected to the conductive connector and the first MLI, and the conductive connector is connected to the second MLI.
6 . The stacked device arrangement of claim 3 , wherein the isolation structure is a first isolation structure and the conductive connector is a first conductive connector, the stacked device arrangement further comprising: a second isolation structure disposed in the first device substrate, the second isolation structure surrounds the first device, and the second isolation structure extends through the first device substrate from a first surface of the first device substrate to a second surface of the first device substrate; and a second conductive connector disposed in the second isolation structure, wherein the second conductive connector is connected to the first device, the second conductive connector is connected to the second device, and the second conductive connector extends from the first surface of the first device substrate to the second surface of the first device substrate.
7 . The stacked device arrangement of claim 6 , wherein: the first MLI provides a frontside of the first chip and the second surface of the first device substrate provides a backside of the first chip; the second MLI provides a frontside of the second chip and the second surface of the second device substrate provides a backside of the second chip; and the backside of the second chip is attached to the backside of the first chip and the first conductive connector is connected to the second conductive connector.
8 . The stacked device arrangement of claim 6 , wherein: the first MLI provides a frontside of the first chip and the second surface of the first device substrate provides a backside of the first chip; the second MLI provides a frontside of the second chip and the second surface of the second device substrate provides a backside of the second chip; and the backside of the second chip is attached to the backside of the first chip by a bonding layer and an interconnect structure of the bonding layer is connected to the first conductive connector and the second conductive connector.
9 . A device stack comprising: a first device over a second device, wherein the first device is formed by a first back-end-of-line (BEOL) structure over a first device layer and the second device is formed by a second BEOL structure over a second device layer; and a trench isolation connector that connects the first device to the second device, wherein the trench isolation connector is a portion of the first device layer, the trench isolation connector has a first thickness that is equal to a second thickness of a semiconductor substrate of the first device layer, the trench isolation connector includes a conductive via disposed in an isolation structure, and the trench isolation connector is a backside interconnect of the first device.
10 . The device stack of claim 9 , wherein the isolation structure is a deep trench isolation structure disposed in the semiconductor-a substrate of the first device layer.
11 . The device stack of claim 9 , wherein the trench isolation connector connects a frontside of the first device to a frontside of the second device.
12 . The device stack of claim 9 , the trench isolation connector is a first trench isolation connector, the backside interconnect is a first backside interconnect, and the conductive via is a first conductive via, the device stack further comprising: a third device formed by the first device layer and the first BEOL structure; a second trench isolation connector that connects the third device to the second device, wherein the second trench isolation connector is a portion of the first device layer, the second trench isolation connector includes a second conductive via disposed in the isolation structure, and the second trench isolation connector is a second backside interconnect of the third device; the first BEOL structure connects a gate of the first device to the first trench isolation connector and a gate of the third device to the second trench isolation connector; and the second BEOL structure connects the first trench isolation connector and the second trench isolation connector.
13 . The device stack of claim 12 , wherein the gate of the first device is a first gate of the first device and the gate of the third device is a first gate of the third device, the first BEOL structure connects the first gate of the first device to a second gate of the first device, and the first BEOL structure connects the first gate of the third device to a second gate of the third device.
14 . The device stack of claim 9 , further comprising a bonding layer that attaches the first device layer and the second BEOL structure, wherein the trench isolation connector is connected to the bonding layer.
15 . The device stack of claim 9 , wherein the first device is a first high voltage transistor and the second device is a second high voltage transistor.
16 . A method for forming a wafer-on-wafer stack comprising: performing front-end-of-line processing on a first wafer and a second wafer, wherein the first wafer includes a first trench isolation structure disposed in a first substrate, the second wafer includes a second trench isolation structure disposed in a second substrate, the first trench isolation structure surrounds a first device of the first wafer, and the second trench isolation structure surrounds a second device of the second wafer; forming a first trench isolation connector in the first trench isolation structure and a second trench isolation connector in the second trench isolation structure; after forming the first trench isolation connector and the second trench isolation connector, forming a first frontside interconnect that connects the first trench isolation structure to the first device and a second frontside interconnect that connects the second trench isolation connector to the second device; and after forming the second frontside interconnect and exposing a backside of the second trench isolation connector, attaching the first wafer to the second wafer, wherein the second trench isolation connector is connected to the first device and the second device.
17 . The method for forming the wafer-on-wafer stack of claim 16 , wherein the first device is a first high voltage transistor and the second device is a second high voltage transistor.
18 . The method for forming the wafer-on-wafer stack of claim 16 , wherein the exposing the backside of the second trench isolation connector includes performing a thinning process on the second wafer.
19 . The method for forming the wafer-on-wafer stack of claim 16 , further comprising directly attaching the first wafer to the second wafer.
20 . The method for forming the wafer-on-wafer stack of claim 16 , further comprising forming a bonding layer and attaching the first wafer to the second wafer via the bonding layer, wherein the second trench isolation connector is connected to the bonding layer.

Description

This application is a non-provisional application of and claims benefit of U.S. Provisional Patent Application Ser. No. 63/342,814, filed May 17, 2022, and U.S. Provisional Patent Application Ser. No. 63/377,281, filed Sep. 27, 2022, the entire disclosures of which are incorporated herein by reference. BACKGROUND The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, denser packing of ICs in advanced IC technology nodes call for denser interconnections between ICs. Although existing interconnection techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects and improvements are needed as IC technologies scale. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A, FIG. 1B, FIG. 2A, FIG. 2B, FIGS. 3A-3C, and FIGS. 4A-4C are various views of a device, in portion or entirety, according to various aspects of the present disclosure. FIGS. 5-9 are fragmentary cross-sectional views of various stacked device structures, in portion or entirety, according to various aspects of the present disclosure. FIG. 10A and FIG. 10B are diagrammatic views of another stacked device structure, in portion or entirety, according to various aspects of the present disclosure. FIG. 11A and FIG. 11B are diagrammatic views of yet another stacked device structure, in portion or entirety, according to various aspects of the present disclosure. FIGS. 12A-12E are fragmentary diagrammatic cross-sectional views of the stacked device structure of FIG. 5, in portion or entirety, at various stages of fabrication thereof according to various aspects of the present disclosure. FIGS. 13A-13E are fragmentary diagrammatic cross-sectional views of the stacked device structure of FIG. 6, in portion or entirety, at various stages of fabrication thereof according to various aspects of the present disclosure. FIGS. 14A-14E are fragmentary diagrammatic cross-sectional views of the stacked device structure of FIG. 7, in portion or entirety, at various stages of fabrication thereof according to various aspects of the present disclosure. FIGS. 15A-15E are fragmentary diagrammatic cross-sectional views of stacked device structure of FIG. 8, in portion or entirety, at various stages of fabrication thereof according to various aspects of the present disclosure. DETAILED DESCRIPTION The present disclosure relates generally to integrated circuit (IC) devices and/or semiconductor devices, and more particularly, to interconnection structures for stacked semiconductor structures and methods of fabrication thereof. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, spatially relative terms, for example, “lower.” “upper.” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up.” “down.” “top.” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly.” “upwardly.” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the ter