US-12622238-B2 - Device and method for fabricating a patterned FD-SOI wafer including exposed buried oxide

Abstract

Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.

Inventors

• Steve Nagel
• Bomy Chen

Assignees

• MICROCHIP TECHNOLOGY INCORPORATED

Dates

Publication Date

20260505

Application Date

20230523

Claims (20)

1. 1 . A device comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate; a SiO 2 layer on the silicon substrate, wherein the SiO 2 layer includes buried oxide (BOX) regions separated by body bias areas in the SiO 2 layer, the body bias areas comprising silicon or polysilicon; and a silicon layer on the SiO 2 layer, wherein the silicon layer covers the body bias areas in the SiO 2 , and wherein respective BOX regions include a main portion and an exposure plug extending from the main portion and exposed through a respective opening in the silicon layer, wherein a respective exposure plug has a box dimension larger than an exposure dimension, wherein the box dimension is near a proximal end connecting with the main portion of the respective BOX region and the exposure dimension is near a distal end of the respective exposure plug.
2. 2 . The device as claimed in claim 1 , wherein the FD-SOI wafer comprises a doped implant in the silicon substrate.
3. 3 . The device as claimed in claim 1 , wherein the respective exposure plug has a trapezoidal-shaped cross-section.
4. 4 . A device by a method, the device comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate comprising a doped implant; a silicon layer having a plurality of openings arranged in a first predetermined pattern; and a SiO 2 layer between the silicon substrate and the silicon layer, wherein the SiO 2 layer has a plurality of body bias areas arranged in a second predetermined pattern to define a plurality of buried oxides (BOXs), whereby the plurality of BOXs are respectively exposed via the plurality of openings, wherein the device is made by a method comprising: preparing a donor silicon wafer comprising: applying a sacrificial SiGe layer on a silicon substrate wafer; depositing a donor silicon layer on the SiGe layer; etching the donor silicon layer to form at least one opening in the silicon layer; wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and preserve the donor silicon layer; depositing an SiO 2 layer on the donor silicon layer; etching the SiO 2 layer to form at least one body bias area; and depositing or growing silicon, or polysilicon, in the at least one body bias area; bonding a recipient handle wafer to the etched SiO 2 layer of the donor silicon wafer, whereby a BOX is defined by the donor silicon layer, the at least one body bias area, and the recipient handle wafer; and wet etching the sacrificial SiGe layer to release the donor silicon wafer from the recipient handle wafer, whereby the SiO 2 layer and the donor silicon layer remain bonded to the recipient handle wafer to form a fully depleted silicon-on-insulator (FD-SOI) wafer.
5. 5 . The device by a method as claimed in claim 4 , wherein depositing the SiO2 layer on the donor silicon layer comprises filling the at least one opening with SiO2 material without bridging oxide material between the silicon substrate wafer and the donor silicon layer.
6. 6 . The device by a method as claimed in claim 4 , comprising polishing the SiO2 layer and the at least one body bias area.
7. 7 . The device by a method as claimed in claim 4 , wherein applying the sacrificial SiGe layer on the silicon substrate wafer comprises epitaxially growing the SiGe layer.
8. 8 . The device by a method as claimed in claim 4 , wherein applying the sacrificial SiGe layer on the silicon substrate wafer produces the sacrificial SiGe layer having a thickness about ten times the thickness of the silicon substrate wafer.
9. 9 . The device by a method as claimed in claim 4 , wherein the at least one opening in the silicon layer comprises a dummy fill opening.
10. 10 . The device by a method as claimed in claim 4 , wherein etching the donor silicon layer to form the at least one opening in the silicon layer comprises etching the silicon layer to form a plurality of openings in the silicon layer in a first predetermined pattern.
11. 11 . The device by a method as claimed in claim 4 , wherein etching the SiO2 layer to form the at least one body bias area comprises etching the buried oxide layer to form a plurality of body bias areas in a second predetermined pattern.
12. 12 . The device by a method as claimed in claim 4 , wherein depositing the SiO2 layer on the donor silicon layer comprises filling the at least one opening with SiO2.
13. 13 . The device by a method as claimed in claim 4 , comprising patterning the sacrificial SiGe layer with a shallow trench isolation mask.
14. 14 . The device by a method as claimed in claim 4 , comprising patterning the SiO2 layer to define the at least one body bias area in the SiO2 layer.
15. 15 . The device by a method as claimed in claim 4 , comprising polishing the SiO2 layer and the at least one body bias area to planarize the SiO2 layer.
16. 16 . The device by a method as claimed in claim 4 , comprising doping an implant in the recipient handle wafer.
17. 17 . The device as claimed in claim 1 , wherein a respective BOX region includes multiple exposure plugs exposed through multiple openings in the silicon layer.
18. 18 . The device as claimed in claim 1 , wherein the silicon layer and the exposure plug have exterior surfaces in the same plane.
19. 19 . The device as claimed in claim 1 , wherein the SiO 2 layer, including the BOX regions separated by body bias areas, has a planarized lower surface in contact with the silicon substrate.
20. 20 . The device as claimed in claim 1 , wherein the openings in the silicon layer comprise openings defining silicon sidewalls having a taper.

Description

RELATED PATENT APPLICATION This application claims priority to commonly owned U.S. Application No. 63/426,657, filed Nov. 18, 2022, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD The present disclosure relates to fully depleted silicon-on-insulator (FD-SOI) wafer production, in particular, production of patterned FD-SOI wafers from standard silicon starting sub state wafers. BACKGROUND Fully depleted silicon-on-insulator (FD-SOI) wafers are also known as ultra-thin or extremely thin silicon-on-insulator (ET-SOI) wafers. Generally, FD-SOI wafers are procured from a substrate manufacturer and then the buried oxide layer (BOX) is patterned and epitaxially grown. This is very costly. Patterned FD-SOI wafers are expensive due to the total process cost, including the cost of the FD-SOI substrates and additional costs associated with etching the patterned buried oxide layer (BOX) areas and regrowing body bias areas by epitaxial (EPI) growth. Traditional methods for creating the FD-SOI wafer result in a continuous buried oxide layer (BOX) and device silicon layer that must be patterned to allow for a top side contact to the body. For example, FD-SOI wafers have a top layer of silicon, so the buried oxide layer (BOX) is unexposed. The buried oxide layer (BOX) should be open or exposed for body biasing. To open or expose the ultra-thin buried oxide (BOX) areas for substrate contacts, the wafers undergo further processing, such as etching. The costs associated with further processing to expose the ultra-thin buried oxide (BOX) areas make the FD-SOI expensive. There is a need for a reduced cost and simplified patterned FD-SOI wafer process that produces FD-SOI wafers with exposed buried oxide layer (BOX) for substrate contacts. SUMMARY OF THE INVENTION Aspects provide methods for production of patterned FD-SOI wafers from standard silicon starting substrate wafers, wherein the methods utilize selective Si/SiGe wet etch chemistries and dual use STI/Release hole patterns to create a pre-patterned FD-SOI wafer. An aspect provides a method comprising: preparing a donor silicon wafer comprising: applying a sacrificial SiGe layer on a silicon substrate wafer; depositing a donor silicon layer on the SiGe layer; etching the donor silicon layer to form at least one opening in the silicon layer; wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and preserve the donor silicon layer; depositing an SiO2 layer on the donor silicon layer; etching the SiO2 layer to form at least one body bias area; and depositing silicon, or polysilicon, in the at least one body bias area; bonding a recipient handle wafer to the etched SiO2 layer of the donor silicon wafer; and wet etching the sacrificial SiGe layer to release the donor silicon wafer from the recipient handle wafer, whereby the SiO2 layer and the donor silicon layer remain bonded to the recipient handle wafer to form a fully depleted silicon-on-insulator (FD-SOI) wafer, wherein the SiO2 layer is a buried oxide layer. According to a further aspect, there is provided a device by a method, the device comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate; a SiO2 layer on the silicon substrate, wherein the SiO2 layer has at least one body bias area; a silicon layer on the SiO2 layer, wherein the silicon layer has at least one opening through which the SiO2 layer is exposed, wherein the device is made by a method comprising: preparing a donor silicon wafer comprising: applying a sacrificial SiGe layer on a silicon substrate wafer; depositing a donor silicon layer on the SiGe layer; etching the donor silicon layer to form at least one opening in the silicon layer; wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and preserve the donor silicon layer; depositing an SiO2 layer on the donor silicon layer; etching the SiO2 layer to form at least one body bias area; and depositing silicon, or polysilicon, in the at least one body bias area; bonding a recipient handle wafer to the etched SiO2 layer of the donor silicon wafer; and wet etching the sacrificial SiGe layer to release the donor silicon wafer from the recipient handle wafer, whereby the SiO2 layer and the donor silicon layer remain bonded to the recipient handle wafer to form a fully depleted silicon-on-insulator (FD-SOI) wafer. Another aspect provides a device by a method, the device comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate comprising a doped implant; a silicon layer having a plurality of openings arranged in a first predetermined pattern; and a SiO2 layer between the silicon substrate and the silicon layer, wherein the SiO2 layer has a plurality of body bias areas arranged