US-12622240-B2 - Dielectric gap fill

US12622240B2US 12622240 B2US12622240 B2US 12622240B2US-12622240-B2

Abstract

Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

Inventors

Yu-Yun Peng

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230731

Claims (20)

1 . A semiconductor device, comprising: a first fin and a second fin protruding from a substrate, a first sidewall of the first fin facing a second sidewall of the second fin, a width being from the first sidewall of the first fin to the second sidewall of the second fin, the width being less than 10 nm; a first dielectric isolation between the first sidewall of the first fin and the second sidewall of the second fin, a top surface of the first dielectric isolation being below a top of the first sidewall or the second sidewall, the first dielectric isolation extending from the first sidewall of the first fin to the second sidewall of the second fin without a void therein, wherein the first dielectric isolation is silicon oxycarbide or silicon oxycarbide nitride with an atomic ratio of oxygen to silicon (O:Si) in the first dielectric isolation is equal to or greater than about 2.0 and with a concentration of carbon in the first dielectric isolation in a range from 5 atomic percent to 16 atomic percent; and a first gate structure disposed over the first dielectric isolation and over the first sidewall of the first fin and the second sidewall of the second fin.
2 . The semiconductor device of claim 1 , further comprising: a third fin and a fourth fin protruding from the substrate; a second dielectric isolation between the third fin and the fourth fin, wherein the second dielectric isolation is a same material as the first dielectric isolation; a third dielectric isolation over the second dielectric isolation between the third fin and the fourth fin; and a second gate structure over the third fin, the fourth fin, the second dielectric isolation, and the third dielectric isolation.
3 . The semiconductor device of claim 2 , wherein the third dielectric isolation is silicon oxycarbide nitride having: an atomic ratio of oxygen to silicon (O:Si) is in a range from 1.3 to 1.9, a concentration of carbon is in a range from 0 atomic percent (at. %) to 20 at. %, and a concentration of nitrogen is in a range from about 0 at. % to about 2 at. %.
4 . The semiconductor device of claim 2 , wherein an upper surface of the first dielectric isolation is level with an upper surface of the second dielectric isolation.
5 . The semiconductor device of claim 4 , wherein an upper surface of the third dielectric isolation is level with an upper surface of the second dielectric isolation.
6 . The semiconductor device of claim 2 , wherein the third dielectric isolation has a k-value of 3.9 to 4.4.
7 . The semiconductor device of claim 6 , wherein the first dielectric isolation and the second dielectric isolation have a k-value of 3.4 to 3.9.
8 . The semiconductor device of claim 1 , wherein the first dielectric isolation has a concentration of nitrogen of less than or equal to 5 at. %.
9 . A semiconductor device, comprising: a first fin and a second fin protruding from a substrate, a first sidewall of the first fin facing a second sidewall of the second fin, a width being from the first sidewall of the first fin to the second sidewall of the second fin, the width being less than 10 nm; a first isolation layer between the first sidewall of the first fin and the second sidewall of the second fin, a top surface of the first isolation layer being below a top of the first sidewall or the second sidewall, the first isolation layer extending from the first sidewall of the first fin to the second sidewall of the second fin without a void therein, wherein the first isolation layer is silicon oxycarbide nitride with an atomic ratio of oxygen to silicon (O:Si) in a range from 1.6 to 1.1 and with a concentration of carbon in a range from 3 atomic percent to 10 atomic percent; and a first gate structure over the first isolation layer and over the first sidewall of the first fin and the second sidewall of the second fin.
10 . The semiconductor device of claim 9 , wherein the first isolation layer has a concentration of nitrogen in a range from 5 atomic percent to 15 atomic percent.
11 . The semiconductor device of claim 9 , further comprising: a third fin and a fourth fin protruding from the substrate, wherein the first isolation layer extends between the third fin and the fourth fin; a second isolation layer over the first isolation layer between the third fin and the fourth fin; and a second gate structure over the first isolation layer, the second isolation layer, the third fin, and the fourth fin.
12 . The semiconductor device of claim 11 , wherein the second isolation layer is silicon oxycarbide nitride.
13 . The semiconductor device of claim 12 , wherein the second isolation layer has: an atomic ratio of oxygen to silicon (O:Si) in a range from 1.3 to 1.9, a concentration of carbon in a range from 0 atomic percent (at. %) to 20 at. %, and a concentration of nitrogen in a range from about 0 at. % to about 2 at. %.
14 . The semiconductor device of claim 12 , wherein the first isolation layer has a k-value of 3.4 to 3.9, and wherein the second isolation layer has a k-value of 3.9 to 4.4.
15 . The semiconductor device of claim 14 , wherein the first isolation layer has a concentration of nitrogen less than or equal to 5 at. %.
16 . A structure comprising: a substrate having a first fin, a second fin, a third fin, and a fourth fin, a distance between the first fin and the second fin being less than 10 nm, a distance between the third fin and the fourth fin being greater than 10 nm; a first dielectric layer between the first fin and the second fin, a top surface of the first dielectric layer being below a top of the first fin and below a top of the second fin, the first dielectric layer extending from the first fin to the second fin without a void therein; a second dielectric layer between the third fin and the fourth fin, a top surface of the second dielectric layer being below a top of the third fin and below a top of the fourth fin, the first dielectric layer and the second dielectric layer being a same material; a third dielectric layer over the second dielectric layer between the third fin and the fourth fin, a top surface of the third dielectric layer being below the top of the third fin and below the top of the fourth fin; a first gate structure over the first fin and the first dielectric layer, wherein a region between the first fin and the second fin and below the first gate structure is free of the third dielectric layer; and a second gate structure over the third fin, the second dielectric layer, and the third dielectric layer.
17 . The structure of claim 16 , wherein the first dielectric layer and the second dielectric layer are silicon oxycarbide or silicon oxycarbide nitride having: an atomic ratio of oxygen to silicon (O:Si) equal to or greater than about 2.0; a concentration of carbon in a range from 5 atomic percent to 16 atomic percent; and a concentration of nitrogen less than or equal to 5 atomic percent.
18 . The structure of claim 16 , wherein the first dielectric layer and the second dielectric layer are silicon oxycarbide nitride having: an atomic ratio of oxygen to silicon (O:Si) in a range from 1.6 to 1.1; a concentration of carbon in a range from 3 atomic percent to 10 atomic percent; and a concentration of nitrogen in a range from about 5 atomic percent to about 15 atomic percent.
19 . The structure of claim 16 , wherein the third dielectric layer is silicon oxycarbide nitride having: an atomic ratio of oxygen to silicon (O:Si) in a range from 1.3 to 1.9; a concentration of carbon in a range from 0 atomic percent to 20 atomic percent; and a concentration of nitrogen in a range from about atomic percent to about 2 atomic percent.
20 . The structure of claim 16 , wherein the first dielectric layer and the second dielectric layer have a dielectric value in a range from 3.4 to 3.9, and wherein the third dielectric layer have a dielectric value in a range from 3.9 to 4.4.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 17/222,012, filed on Apr. 5, 2021, entitled “Dielectric Gap Fill,” which is a continuation of U.S. patent application Ser. No. 16/007,161, filed on Jun. 13, 2018, entitled “Dielectric Gap Fill,” which applications are hereby incorporated herein by reference. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Accompanying the scaling down of devices, manufacturers have begun using new and different materials and/or combination of materials to facilitate the scaling down of devices. Scaling down, alone and in combination with new and different materials, has also led to challenges that may not have been presented by previous generations at larger geometries. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1B, 2, 3, 4, 5A-5B, 6, 7A-7B, and 8A-8B are views of respective intermediate structures at respective stages during an example process for forming Fin Field Effect Transistors (FinFETs) in accordance with some embodiments. FIGS. 9 through 14 are schematic illustrations of compounds of various precursor gases. FIG. 15 is a flowchart of a method for filling one or more trenches in accordance with some embodiments. FIG. 16 is a flowchart of a method for filling one or more trenches in accordance with some embodiments. FIG. 17 is a flowchart of a method for filling one or more trenches in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Generally, the present disclosure provides example embodiments relating to filling gaps with a dielectric material. More specifically, example embodiments described herein relate to filling gaps having narrow dimensions with a dielectric material without a seam or void being formed in the dielectric material. In some examples, an atomic layer deposition (ALD) process is used to deposit a dielectric material in a gap, such as a trench between fins. A subsequent process converts the dielectric material to another dielectric material. As examples, the subsequent process may include an anneal in an oxygen-containing ambient, a gas soak in an oxygen-containing ambient, a plasma containing oxygen, and/or an ultraviolet (UV) treatment in an oxygen-containing ambient. The converted dielectric material may fill the gap without a seam or void formed therein in some examples. In examples where the converted dielectric material is formed in trenches between fins, bending of the