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US-12622241-B2 - Structures with convex cavity bottoms

US12622241B2US 12622241 B2US12622241 B2US 12622241B2US-12622241-B2

Abstract

Provided are conductive structures located within dielectric material, and methods for fabricating such structures and devices. An exemplary method includes providing a substrate having a conductive feature in a first dielectric layer; depositing a second dielectric layer over the conductive feature and the first dielectric layer; etching the second dielectric layer to form a cavity through the second dielectric layer, wherein the cavity has a bottom with a convex profile; depositing a barrier layer along the bottom of the cavity; and depositing a conductive material in the cavity to form a structure electrically connected to the conductive feature.

Inventors

  • Yu-Lien Huang
  • Wei Hsiang Chan

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260505
Application Date
20230118

Claims (20)

  1. 1 . A method comprising: performing an etching process to etch a material to form a trench bound by a trench sidewall formed from the material and a convex trench bottom surface formed from the material, wherein the material has an upper surface, wherein the trench sidewall extends downward from the upper surface and intersects the convex trench bottom surface at a trench corner at a first depth below the upper surface; etching the material through a portion of the convex trench bottom surface to form a via bound by a via sidewall; depositing a barrier layer along the trench sidewall, along remaining portions of the convex trench bottom surface, and along the via sidewall, wherein a convex profile of the convex trench bottom surface is configured to facilitate formation of the barrier layer as a continuous barrier layer without voids or disconnections at the trench corner; and forming a conductive structure over the barrier layer in the trench and the via.
  2. 2 . The method of claim 1 , wherein the trench sidewall and the convex trench bottom surface form an angle of at least 60° at the trench corner.
  3. 3 . The method of claim 1 , wherein the etching process comprises a plasma etching process performed with an RF bias power of from 10 to 500 watts, with an ionization energy of from 10 to 500 electronvolts (eV), and with a dilution gas comprising argon (Ar) such that ions reflect from the trench sidewall on incidence and re-impinge on the material adjacent to the trench sidewall to form the convex trench bottom surface.
  4. 4 . The method of claim 1 , wherein the convex trench bottom surface is formed only from the material.
  5. 5 . The method of claim 1 , wherein the etching process comprises plasma etching using an inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) etching tool at a pressure of from 3 to 150 milliTorr and with argon dilution gas.
  6. 6 . The method of claim 1 , wherein: no structure or sublayer within the material is formed with the convex trench bottom surface before the etching process begins; and the etching process etches ends of the convex trench bottom surface at a faster rate than the etching process etches a central portion of the convex trench bottom surface to form the convex profile.
  7. 7 . A method comprising: providing a substrate having a dielectric layer; and performing an etching process to etch the dielectric layer to form a cavity with a sidewall and having a bottom with a convex profile, wherein the etching process comprises a plasma etching process performed with a pressure of from 3 to 150 milliTorr (mTorr), a temperature of from −80 to 140° C., and a RF bias power of greater than 30 watts that causes ions to reflect from the sidewall and re-impinge on the dielectric layer adjacent to the sidewall to form micro-trenching, and wherein the convex profile of the bottom results from the micro-trenching.
  8. 8 . The method of claim 7 , wherein the bottom of the cavity is formed by the dielectric layer.
  9. 9 . The method of claim 7 , wherein the cavity has a critical dimension (CD) of from about 10 nm to about 200 nm.
  10. 10 . The method of claim 7 , wherein performing the etching process comprises forming the cavity with the sidewall intersecting the bottom at an angle of at least 60°.
  11. 11 . The method of claim 7 , wherein performing the etching process comprises forming the cavity with a first sidewall intersecting a first end of the bottom at a first internal angle and with a second sidewall intersecting a second end of the bottom at a second internal angle; and wherein a difference between the first internal angle and the second internal angle is no more than 2°.
  12. 12 . The method of claim 7 , wherein etching performing the etching process comprises forming the cavity with a depth from about 30 nm to about 50 nm.
  13. 13 . The method of claim 7 , further comprising forming a barrier layer overlying an exposed surface of the cavity, resulting in a lined cavity.
  14. 14 . The method of claim 13 , further comprising filling the lined cavity with a metal material.
  15. 15 . The method of claim 7 , wherein performing the etching process comprises etching the dielectric layer to form a trench and etching the dielectric layer to form a via, wherein the cavity is a via-trench cavity and wherein, after etching the dielectric layer to form the trench and after etching the dielectric layer to form the via, the via extends from the bottom of the trench through the dielectric layer to a metal contact.
  16. 16 . The method of claim 15 , further comprising: forming a barrier layer overlying an exposed surface of the via-trench cavity, resulting in a lined via-trench cavity; and filling the lined via-trench cavity with a metal material.
  17. 17 . A method comprising: performing an etching process to etch a material to form a first trench bound by a first trench sidewall formed from the material and a first convex trench bottom surface formed from the material and to form a second trench bound by a second trench sidewall formed from the material and a second convex trench bottom surface formed from the material, wherein the first trench has a first width and the second trench has a second width, wherein a ratio of the first width to the second width is from 1.5:1 to 20:1.
  18. 18 . The method of claim 17 , wherein the etching process is a plasma etching process performed with an RF bias power of from 10 to 500 watts and an ionization energy of from 10 to 500 electronvolts (eV) such that ions reflect from the respective trench sidewalls on incidence and re-impinge on the material adjacent to the respective sidewalls to form the respective convex trench bottom surfaces.
  19. 19 . The method of claim 18 , wherein the plasma etching process is performed with a dilution gas comprising argon (Ar).
  20. 20 . The method of claim 19 , wherein the plasma etching process is performed with an inductively coupled plasma (ICP) or a capacitively couple plasma (CCP) etching tool with a pressure of from 3 to 150 milliTorr (mTorr), a temperature of from −80 to 140° C., and a RF bias power of greater than 30 watts.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Application No. 63/375,804, filed Sep. 15, 2022. BACKGROUND The scaling down of semiconductor devices has led to challenges that may not have been presented by previous generations at larger geometries. For example, metal line (e.g., copper) gap fill becomes more challenging at scaled down dimensions due to increased aspect ratios of cavities such as vias and trenches. Further, in dual damascene processing the spacing between vias and trenches is getting smaller. Formation of barrier layers, such as TaN, on trench profiles may be increasingly difficult at scaled down dimensions. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-10 are cross-sectional schematic views of a portion of a semiconductor structure during sequential stages of a fabrication process for forming a via-trench cavity in accordance with some embodiments. FIGS. 11-20 are cross-sectional schematic views of a portion of a semiconductor structure during sequential stages of a fabrication process for forming a via-trench cavity in accordance with some embodiments. FIGS. 21 and 22 are cross-sectional schematic views of a trench cavity etched into a material in accordance with the processes of FIGS. 1-10 or FIGS. 11-20. FIGS. 23 and 24 are cross-sectional schematic views of further processing of the trench cavity of FIGS. 21 and 22 in accordance with some embodiments. FIGS. 25-26 are cross-sectional schematic views of processing of a via-trench cavity in accordance with the processes of FIGS. 1-10 or FIGS. 11-20. FIG. 27 is a cross-sectional schematic view of another embodiment of a via-trench cavity in accordance with some embodiments. FIG. 28 is a cross-sectional schematic view of a plurality of conductive interconnects formed in trench and via-trench cavities in a dielectric layer in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “beneath”, “below”, “lower”, “bottom”, “side”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer. In certain embodiments herein, a “material layer” is a layer that includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, or at least 75 wt. % of the identified material, or at least 90 wt. % of the identified material; and a layer that is a “material” includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, or at least 90 wt. % of the identified material. For example, certain embodiments, each of a titanium nitride layer and a layer that is titanium nitride is a layer that is at least 50 wt. %, at least 60 wt. %, at least 75 wt. %