US-12622242-B2 - Selective self-assembled monolayer (SAM) removal

Abstract

Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.

Inventors

• Jiajie Cen
• Zhiyuan Wu
• Kevin Kashefi
• Yong Jin Kim
• Yang Zhou
• Zheng JU

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260505

Application Date

20230613

Claims (19)

1. 1 . A method of forming a microelectronic device, the method comprising: forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom; forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask, the plasma comprising one or more of hydrogen (H 2 ) or Argon (Ar); forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner, wherein treating the microelectronic device with the plasma comprises increasing a density of the barrier layer.
2. 2 . The method of claim 1 , wherein the metal liner is deposited at a thickness on the sidewalls that is greater than a thickness of the metal liner deposited on the bottom.
3. 3 . The method of claim 1 , wherein the metal liner is deposited on the sidewalls and not on the bottom.
4. 4 . The method of claim 1 , wherein selectively depositing the SAM comprises exposing the bottom of the gap and the hardmask to a hydrocarbon carried in an argon (Ar) gas.
5. 5 . The method of claim 1 , further comprising removing the SAM from the bottom of the gap after forming the barrier layer on the dielectric layer and the hardmask.
6. 6 . The method of claim 1 , wherein the hardmask comprises one or more of tungsten carbide (WC), titanium nitride (TiN), oxides, and nitrides.
7. 7 . The method of claim 1 , wherein the metal liner comprises one or more of ruthenium (Ru), cobalt (cobalt), molybdenum (Mo), and tantalum (Ta).
8. 8 . The method of claim 7 , wherein the metal liner comprises a single layer of ruthenium (Ru).
9. 9 . The method of claim 7 , wherein the selective ruthenium (Ru) deposition on the sidewall comprises a cyclic deposition process using a ruthenium (Ru) precursor carried by an argon (Ar) gas to form a deposited ruthenium layer.
10. 10 . The method of claim 9 , wherein the cyclic deposition process further comprises annealing the deposited ruthenium layer while flowing hydrogen (H 2 ) and annealing the deposited ruthenium layer.
11. 11 . The method of claim 10 , wherein the cyclic deposition process is performed in a substrate processing chamber at a first pressure to form the deposited ruthenium layer, and annealing the deposited ruthenium layer is performed while the substrate processing chamber is at a second pressure that is greater than the first pressure.
12. 12 . The method of claim 1 , wherein the gap fill process comprises filling the gap with one or more of copper (Cu) or cobalt (Co).
13. 13 . The method of claim 1 , wherein the plasma treatment comprises treating the microelectronic device with a plasma in a depletion mode.
14. 14 . The method of claim 13 , herein the plasma comprises hydrogen (H 2 ).
15. 15 . The method of claim 13 , wherein the plasma is a remote plasma.
16. 16 . The method of claim 13 , wherein the plasma is a capacitively coupled plasma with a pulsed hydrogen (H 2 ) supply.
17. 17 . The method of claim 13 , wherein the depletion mode comprises a low pressure and an abbreviated time treatment.
18. 18 . A method of forming a microelectronic device, the method comprising: forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom; forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a hydrogen (H 2 ) plasma in a depletion mode to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask, wherein treating the microelectronic device with the hydrogen (Ha) plasma comprises increasing a density of the barrier layer; removing the SAM from the bottom of the gap; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.
19. 19 . The method of claim 18 , wherein the depletion mode comprises a low pressure and a short time treatment.

Description

TECHNICAL FIELD Embodiments of the disclosure generally relate to methods of forming a metal liner for interconnect structures. More particularly, embodiments of the disclosure are directed to methods of selectively removing a self-assembled monolayer (SAM) for controlling barrier and liner deposition. BACKGROUND Multiple challenges impede power and performance improvements when scaling transistors and interconnects to the 3 nm node, 2 nm node, 1.4 nm node, and beyond. Interconnects include metal lines that transfer current within the same device layer and metal vias that transfer current between layers. Pitch reduction narrows the width of both and increases resistance, and also increases the voltage drop across a circuit, throttling circuit speed and increasing power dissipation. While transistor performance improves with scaling, the same cannot be said for interconnect metals. As dimensions shrink, interconnect via resistance can increase by a factor of 10. An increase in interconnect via resistance may result in resistive-capacitive (RC) delays that reduce performance and increases power consumption. A conventional copper interconnect structure includes a barrier layer and/or a metal liner deposited on the sidewalls of gap that provide a via the sidewalls made of a dielectric material, providing good adhesion, and preventing the copper from diffusing into the dielectric layer. Barrier layers can typically be the largest contributor to via resistance due to high resistivity. Past approaches have focused on reducing the thickness of barrier layers or finding barrier layers with lower resistivity to decrease via resistance. Increased via resistance remains an issue, especially in smaller features when barrier layers on sidewalls form an increasing percentage of the via volume. The use of selective liners and 1-layer barrier-liners provides great potential for barrier/liner thinning down and Rc improvement. Copper (Cu) gap-fill has been facing challenges over narrower and narrower structures with high aspect ratios as the Cu interconnect nodes advances towards 2 nm, 1.4 nm, and beyond. Tungsten carbide (WC) hard masks prevent proper barrier and liner deposition and impact Cu reflow. Accordingly, there is a need for methods for depositing material layers that improve performance of interconnects, for example, reducing via resistance and improving deposition selectivity. SUMMARY Embodiments of the disclosure are directed to methods of forming a microelectronic device. In one or more embodiments, the method comprises: forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom; forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner. Further embodiments of the disclosure are directed to methods of forming a microelectronic device. In one or more embodiments, the method comprises: forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom; forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a hydrogen (H2) plasma in depletion mode to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; removing the SAM from the bottom of the gap; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. FIG. 1 illustrates a process flow diagram of a method of manufacturing a microelectronic device in accordance with one or more embodiments of the disclosure; FIG. 2A illustrates a cross-sectional view of portion of a microelectronic device during a stage of manufacture in accordance with one or more embodiments of the disclosure; FIG. 2B illustrates a cross-sectional view of portion of a microelectronic device during a stage of manufacture in acc