US-12622243-B2 - Selective liner deposition for via resistance reduction

Abstract

Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.

Inventors

• Yang Zhou
• Jiajie Cen
• Zhiyuan Wu
• Ge Qu
• Yong Jin Kim
• Zheng JU
• Feng Chen
• Kevin Kashefi

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260505

Application Date

20230619

Claims (20)

1. 1 . A method of forming a microelectronic device, the method comprising: passivating a metal material at a bottom of a gap with an alkyl reactant comprising one or more of an alkyl halide or an alkyl pseudohalide to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising a dielectric material having a barrier layer thereon; and selectively depositing a metal liner on the barrier layer.
2. 2 . The method of claim 1 , wherein the metal material comprises one or more of ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), tantalum (Ta), or tungsten (W).
3. 3 . The method of claim 1 , wherein the barrier layer comprises tantalum nitride (TaN).
4. 4 . The method of claim 1 , further comprising: selectively depositing the barrier layer on the dielectric material over the metal material.
5. 5 . The method of claim 4 , wherein selectively depositing the barrier layer comprises forming a self-assembled monolayer (SAM) on the metal material, depositing the barrier layer on the sidewalls of the gap, and removing the SAM.
6. 6 . The method of claim 1 , wherein the alkyl reactant is the alkyl halide.
7. 7 . The method of claim 6 , wherein the alkyl halide has a general formula RX, wherein R is an alkyl group having 1 to 20 carbon atoms and X is a halogen comprising one or more of F, CI, Br, I, or CF 3 .
8. 8 . The method of claim 1 , wherein the alkyl reactant is the alkyl pseudohalide.
9. 9 . The method of claim 8 , wherein the alkyl pseudohalide has a general formula of Ps-Ps or Ps-X, where Ps is a pseudohalogen group comprising one or more of cyanide (—CN), cyanate (—OCN), carbonyl (—CO), thiocyanate (—SCN), azide (—Ns), isocyanate (—NCO), isothiocyanate (—NCS), selenocyanate (—SeCN), or isoselenocyanate (—NCSe), and X is a halogen comprising one or more of F, CI, Br, I, or CF 3 .
10. 10 . The method of claim 1 , wherein the metal liner comprises one or more of ruthenium (Ru), cobalt (cobalt), molybdenum (Mo), or tantalum (Ta).
11. 11 . The method of claim 10 , wherein the metal liner consists essentially of ruthenium and a selectivity of the metal liner deposition is greater than or equal to 5.
12. 12 . The method of claim 11 , wherein the metal liner is deposited by chemical vapor deposition.
13. 13 . The method of claim 1 , further comprising removing the passivation layer by exposing the microelectronic device to hydrogen (H 2 ).
14. 14 . The method of claim 13 , wherein exposing the microelectronic device to hydrogen (H 2 ) comprises exposing the microelectronic device to a thermal hydrogen (H 2 ) soak.
15. 15 . The method of claim 13 , wherein exposing the microelectronic device to hydrogen (H 2 ) comprises exposing the microelectronic device to a H 2 plasma treatment.
16. 16 . The method of claim 13 , further comprising a gap fill process to fill the gap with one or more of copper (Cu), cobalt (Co), or tungsten (W).
17. 17 . The method of claim 1 , wherein the method reduces a resistance of a via by at least 20% as compared to a resistance of a via in a microelectronic device where a metal liner is not selectively deposited.
18. 18 . A method of forming a microelectronic device, the method comprising: forming a dielectric material on a substrate, the dielectric material comprising at least one feature defining a gap including sidewalls and a bottom, the bottom comprising a metal material; selectively depositing a self-assembled monolayer (SAM) on the metal material; depositing a barrier layer on the sidewalls of the gap; removing the self-assembled monolayer (SAM) to expose the metal material; passivating the metal material with one or more of an alkyl halide or an alkyl pseudohalide to form a passivation layer on the metal material; and selectively depositing a metal liner on the barrier layer.
19. 19 . The method of claim 18 , wherein the alkyl halide has a general formula RX, wherein R is an alkyl group having 1 to 20 carbon atoms and X is a halogen comprising one or more of F, CI, Br, I, CF 3 , and wherein the alkyl pseudohalide has a general formula of Ps-Ps or Ps-X, where Ps is a pseudohalogen group comprising one or more of cyanide (—CN), cyanate (—OCN), carbonyl (—CO), thiocyanate (—SCN), azide (—N 3 ), isocyanate (—NCO), isothiocyanate (—NCS), selenocyanate (—SeCN), or isoselenocyanate (—NCSe), and X is a halogen comprising one or more of F, CI, Br, I, or CF 3 .
20. 20 . The method of claim 18 , wherein the metal liner is deposited with a selectivity of greater than or equal to 5.

Description

TECHNICAL FIELD Embodiments of the disclosure generally relate to methods of forming a metal liner for interconnect structures. More particularly, embodiments of the disclosure are directed to methods of selectively depositing a metal liner layer. BACKGROUND Multiple challenges impede power and performance improvements when scaling transistors and interconnects to the 3 nm node and beyond. Interconnects include metal lines that transfer current within the same device layer and metal vias that transfer current between layers. Pitch reduction narrows the width of both and increases resistance, and also increases the voltage drop across a circuit, throttling circuit speed and increasing power dissipation. While transistor performance improves with scaling, the same cannot be said for interconnect metals. As dimensions shrink, interconnect via resistance can increase by a factor of 10. An increase in interconnect via resistance may result in resistive-capacitive (RC) delays that reduce performance and increase power consumption. A conventional copper interconnect structure includes a barrier layer and/or a metal liner deposited on the sidewalls of gap that provide a via the sidewalls made of a dielectric material, providing good adhesion, and preventing the copper from diffusing into the dielectric layer. Barrier layers can typically be the largest contributor to via resistance due to high resistivity. Past approaches have focused on reducing the thickness of barrier layers or finding barrier layers with lower resistivity to decrease via resistance. Increased via resistance remains an issue, especially in smaller features when barrier layers on sidewalls form an increasing percentage of the via volume. A metal liner deposited on a barrier layer adheres to the barrier layer and facilitates subsequent copper (Cu) fill in a gap between the sidewalls. Current approaches focus on selectively growing a metal liner on a via sidewall versus the via bottom with high selectivity in an attempt to reduce via resistance and Cu corrosion, through selective growth remains a challenge. Accordingly, there is a need for methods for depositing material layers that improve performance of interconnects, for example, reducing via resistance and improving deposition selectivity. SUMMARY Embodiments of the disclosure are directed to methods of forming a microelectronic device. In one or more embodiments, the method of forming a microelectronic device comprises: passivating a metal material at a bottom of a gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising a dielectric material having a barrier layer thereon; and selectively depositing a metal liner on the barrier layer. Further embodiments are directed to a method of forming a microelectronic device. In one or more embodiments, the method comprises: forming a dielectric material on a substrate, the dielectric material comprising at least one feature defining a gap including sidewalls and a bottom, the bottom comprising a metal material; selectively depositing a self-assembled monolayer (SAM) on the metal material; depositing a barrier layer on the sidewalls of the gap; removing the self-assembled monolayer (SAM) to expose the metal material; passivating the metal material with one or more of an alkyl halide or an alkyl pseudohalide to form a passivation layer on the metal material; and selectively depositing a metal liner on the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. FIG. 1 illustrates a process flow diagram of a method of manufacturing a microelectronic device in accordance with one or more embodiments of the disclosure; FIG. 2A illustrates a portion of a microelectronic device during a stage of manufacture in one or more embodiments of the disclosure; FIG. 2B illustrates a portion of a microelectronic device during a stage of manufacture in one or more embodiments of the disclosure; FIG. 2C illustrates a portion of a microelectronic device during a stage of manufacture in one or more embodiments of the disclosure; FIG. 2D illustrates a portion of a microelectronic device during a stage of manufacture in one or more embodiments of the disclosure; FIG. 2E illustrates a portion of a microelectronic device during a stage of manufacture in one or more embodiments of the disclosure; and FIG. 2F illustrates a portion of a microelectronic device during a stage of manufacture in one or mo