US-12622246-B2 - Mandrel-pull-first interconnect patterning

Abstract

A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

Inventors

• Xiaoming Yang
• Yann Mignot
• Somnath Ghosh
• Daniel Charles Edelstein

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20221110

Claims (13)

1. 1 . A semiconductor structure comprising: a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity where, in the portion of the cavity filled with the spin-on glass, the spin-on glass directly contacts the spacer.
2. 2 . The semiconductor structure of claim 1 , wherein the substrate comprises a tetraethylorthosilicate hard mask under the spacer.
3. 3 . The semiconductor structure of claim 2 , wherein the tetraethylorthosilicate hard mask is about 10 nm thick.
4. 4 . The semiconductor structure of claim 2 , wherein a trench is etched into the tetraethylorthosilicate hard mask under the portion of the cavity that is not filled by the spin-on glass.
5. 5 . The semiconductor structure of claim 4 , wherein the substrate further comprises a titanium nitride hard mask, and wherein the trench is etched into the titanium nitride hard mask.
6. 6 . The semiconductor structure of claim 5 , wherein the titanium nitride hard mask is about 20 nm thick.
7. 7 . The semiconductor structure of claim 1 , wherein the substrate comprises a base layer of silicon carbonitride.
8. 8 . The semiconductor structure of claim 7 , wherein the base layer is about 8 nm thick.
9. 9 . The semiconductor structure of claim 1 , wherein the substrate comprises a body layer of silicon cyanate.
10. 10 . The semiconductor structure of claim 9 , wherein the body layer is about 40 nm thick.
11. 11 . The semiconductor structure of claim 1 , wherein the substrate comprises a covering layer of silicon nitride.
12. 12 . The semiconductor structure of claim 11 , wherein the covering layer is about 20 nm thick.
13. 13 . The semiconductor structure of claim 1 , wherein the spacer fully surrounds the cavity.

Description

BACKGROUND The present invention relates to the electrical, electronic, and computer arts, and more specifically, to fabricating semiconductor devices. Conventionally, metal traces in the interconnect layers of modern semiconductor devices are formed by a process known as self-aligned double patterning (SADP). SADP uses iterative deposition techniques to overcome the known problem that modern feature sizes are too small to be accurately formed using photolithographic techniques alone. That is, current process nodes have sub-wavelength features that are smaller than the extreme ultraviolet (EUV) wavelength that is used for photolithography. SADP uses sacrificial spacers to reduce the feature size to approximately half of the minimum size that can be achieved using EUV photolithography. FIG. 1 depicts, in a photomicrograph, metal traces 100 that were formed in a substrate 102 by self-aligned double patterning, according to the prior art. There are bumps 104, 106 on the sides of “non-mandrel” traces 108, 110. The bumps 104, 106 were produced due to the phenomenon of “spacer pinch-off” In extreme cases, the bumps 104, 106 can extend across the gaps 112, 114 that separate the traces 116, 118, 120. If the bumps extend across the gaps, they form what are called “non-mandrel line bridges.” This occurs when the gaps are too broad. On the other hand, if a gap (e.g., gap 112) is too narrow, then the spacer does not properly pinch off, and there will be a “mandrel line bridge” 122 between, e.g., trace 116 and trace 118. FIG. 2 depicts, in a schematic, a spacer pinch off step 200 of a prior art process that is used for forming the metal traces 100 that are shown in FIG. 1. Note the spacers 202 surround mandrels 204. Gaps 206 between the mandrels (mandrel cuts) were previously formed by etching, e.g., photolithography. The mandrels 204 will later be replaced by metal mandrel lines, such as the traces 116, 118, 120 that are shown in FIG. 1. Non-mandrel gaps 208 between the spacers 202 will later be replaced by non-mandrel lines, such as the traces 108, 110 that are shown in FIG. 1. As an inherent artifact of the deposition process that was used to form the spacers 202, at each gap 206, the spacers have indentations 210. When traces are formed in the non-mandrel gaps 208, indentations such as the indentations 210 will produce bumps such as the bumps 104, 106. The ordinary skilled worker will appreciate that widening the gaps 206 would enlarge the indentations 210 and the bumps 104, 106, which could result in non-mandrel line bridges. Further, narrowing the gaps 206 could prevent the spacers 202 fully filling the gaps, which could result in mandrel line bridges. It is not possible to replicate the critical dimensions of mandrel cuts and the thickness of spacers across the entirety of a wafer. Therefore, the process variation inevitably produces line bridges that detract from product yield. SUMMARY Principles of the invention provide techniques for mandrel-pull-first interconnect patterning. In one aspect, an exemplary method includes obtaining a preliminary structure that includes a substrate, a mandrel protruding from the substrate, and a spacer surrounding the mandrel; forming a first structure, which includes the substrate with the spacer protruding from the substrate and surrounding a cavity, by pulling the mandrel from the preliminary structure; forming a second structure by depositing a first organic planarization layer (OPL) onto the first structure, etching a first non-mandrel cut into the first OPL at a position that is not aligned in registry with the cavity of the spacer, depositing a filler into the first non-mandrel cut, ashing the first OPL, and etching back the filler; forming a third structure by depositing a second OPL onto the second structure, etching a second non-mandrel cut and a mandrel cut into the second OPL, wherein the mandrel cut is at a position that is aligned in registry with the cavity of the spacer, filling the second non-mandrel cut and the mandrel cut with spin-on glass, and ashing the second OPL; forming a fourth structure by opening a top hard mask of the substrate in predetermined areas not covered by the spacer, the filler, and the spin-on glass, then opening a lower hard mask of the substrate in the predetermined areas, then etching trenches in the same areas through a covering layer of the substrate and into a dielectric body of the substrate, then removing the hard masks; and forming a metallized structure in the body of the substrate by filling a metal into the trenches of the fourth structure. The metal does not fill the trenches in areas that were covered by the spacer, the filler, and the spin-on glass. According to another aspect, a semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity. In view of the foregoing, techniques of the present invention can provide substantial be