US-12622248-B2 - Interconnects with sidewall barrier layer divot fill

Abstract

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

Inventors

• Koichi Motoyama
• Oscar van der Straten
• Chih-Chao Yang

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20221212

Claims (19)

1. 1 . An interconnect structure, comprising: a first interlayer dielectric disposed on a wafer; at least one metal line embedded in the first interlayer dielectric, wherein a top surface of the at least one metal line is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; at least one conductive via embedded in the second interlayer dielectric, wherein the at least one conductive via is aligned with the at least one metal line; a barrier layer along a bottom and a first portion of a sidewall of the at least one metal line; a protective dielectric layer along a second portion of the sidewall of the at least one metal line, wherein the barrier layer and the protective dielectric layer fully separate the at least one metal line from the first interlayer dielectric; and a liner between and physically separating an entirety of the at least one metal line from the protective dielectric layer.
2. 2 . The interconnect structure of claim 1 , wherein the protective dielectric layer comprises a different material from the barrier layer.
3. 3 . The interconnect structure of claim 1 , wherein the protective dielectric layer comprises a material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.
4. 4 . The interconnect structure of claim 1 , wherein the barrier layer comprises a material selected from the group consisting of: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and combinations thereof.
5. 5 . The interconnect structure of claim 1 , wherein the liner comprises a material selected from the group consisting of: cobalt (Co), tungsten (W), ruthenium (Ru), and combinations thereof.
6. 6 . The interconnect structure of claim 1 , further comprising: a dielectric cap disposed on the first interlayer dielectric that separates the first interlayer dielectric from the second interlayer dielectric.
7. 7 . The interconnect structure of claim 6 , wherein the dielectric cap comprises a material selected from the group consisting of: aluminum oxide (AlOx), SiN, silicon carbide (SiC), SiCN, silicon oxycarbide (SiCO), SiON, and combinations thereof.
8. 8 . An interconnect structure, comprising: a first interlayer dielectric disposed on a wafer; at least one metal line embedded in the first interlayer dielectric, wherein a top surface of the at least one metal line is recessed below a top surface of the first interlayer dielectric; a metal cap disposed on the at least one metal line; a second interlayer dielectric disposed on the first interlayer dielectric; at least one conductive via embedded in the second interlayer dielectric, wherein the at least one conductive via is aligned with the at least one metal line; a barrier layer along a bottom and a first portion of a sidewall of the at least one metal line; and a protective dielectric layer along a second portion of the sidewall of the at least one metal line, wherein the barrier layer and the protective dielectric layer fully separate the at least one metal line from the first interlayer dielectric, and wherein a top surface of the protective dielectric layer directly contacts a bottom surface of the metal cap.
9. 9 . The interconnect structure of claim 8 , wherein the metal cap comprises a material selected from the group consisting of: Co, Ru, and combinations thereof.
10. 10 . The interconnect structure of claim 8 , wherein the protective dielectric layer comprises a different material from the barrier layer.
11. 11 . The interconnect structure of claim 8 , wherein the protective dielectric layer comprises a material selected from the group consisting of: SiN, SiON, SiCN, SiOCN, and combinations thereof.
12. 12 . The interconnect structure of claim 8 , wherein the barrier layer comprises a material selected from the group consisting of: Ti, Ta, TiN, TaN, and combinations thereof.
13. 13 . The interconnect structure of claim 8 , further comprising: a dielectric cap disposed on the first interlayer dielectric that separates the first interlayer dielectric from the second interlayer dielectric.
14. 14 . The interconnect structure of claim 13 , wherein the dielectric cap comprises a material selected from the group consisting of: AlOx, SiN, SiC, SiCN, SiCO, SiON, and combinations thereof.
15. 15 . The interconnect structure of claim 1 , wherein a top surface of the protective dielectric layer directly contacts a bottom surface of a second barrier layer of the at least one conductive via.
16. 16 . The interconnect structure of claim 1 , wherein a top surface of the protective dielectric layer is substantially flush with a top surface of the at least one metal line.
17. 17 . The interconnect structure of claim 6 , wherein a top surface of the protective dielectric layer directly contacts a bottom surface of the dielectric cap.
18. 18 . The interconnect structure of claim 8 , further comprising: a liner physically separating the at least one metal line from both the protective dielectric layer and the barrier layer, wherein a top surface of the liner directly contacts the bottom surface of the metal cap.
19. 19 . The interconnect structure of claim 8 , wherein the top surface of the protective dielectric layer is substantially flush with the top surface of the at least one metal line.

Description

BACKGROUND The present invention relates to semiconductor device interconnects, and more particularly, to dual damascene, fully aligned via interconnects where barrier layer divots are filled with dielectric material. Interconnects in a semiconductor device serve as connections between various components, both horizontally and vertically amongst different levels of the device design. Interconnects are often formed from conductors such as copper using a so-called dual-damascene process. Fully aligned via techniques have been proposed to reduce interconnect resistance by confining the via to the metal line below. Doing so, however, can undesirably lead to breaks in the sidewall barrier alongside the metal line, forming pathways for copper to diffuse into the surrounding dielectric. Diffusion of copper into the surrounding dielectric causes leakage issues. Therefore, dual damascene techniques for forming fully aligned vias with complete sidewall protection to prevent metal diffusion would be desirable. SUMMARY The present invention provides dual damascene, fully aligned via interconnects where divots in the barrier layer are filled with dielectric material. In one aspect of the invention, an interconnect structure is provided. The interconnect structure includes: a first interlayer dielectric disposed on a wafer; at least one metal line embedded in the first interlayer dielectric, where a top surface of the at least one metal line is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; at least one conductive via embedded in the second interlayer dielectric, where the at least one conductive via is aligned with the at least one metal line; a barrier layer along a bottom and a first portion of a sidewall of the at least one metal line; and a protective dielectric layer along a second portion of the sidewall of the at least one metal line, where the barrier layer and the protective dielectric layer fully separate the at least one metal line from the first interlayer dielectric. For instance, the protective dielectric layer can include a material selected from: silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. In another aspect of the invention, another interconnect structure is provided. The interconnect structure includes: a first interlayer dielectric disposed on a wafer; at least one metal line embedded in the first interlayer dielectric, where a top surface of the at least one metal line is recessed below a top surface of the first interlayer dielectric; a metal cap disposed on the at least one metal line; a second interlayer dielectric disposed on the first interlayer dielectric; at least one conductive via embedded in the second interlayer dielectric, where the at least one conductive via is aligned with the at least one metal line; a barrier layer along a bottom and a first portion of a sidewall of the at least one metal line; and a protective dielectric layer along a second portion of the sidewall of the at least one metal line, where the barrier layer and the protective dielectric layer fully separate the at least one metal line from the first interlayer dielectric. In yet another aspect of the invention, a method of fabricating an interconnect structure is provided. The method includes: depositing a first interlayer dielectric onto a wafer; forming at least one metal line in the first interlayer dielectric, where the at least one metal line is separated from the first interlayer dielectric by a barrier layer; recessing the at least one metal line such that a top surface of the at least one metal line is below a top surface of the first interlayer dielectric, where the recessing creates divots in the barrier layer; forming a protective dielectric layer in the divots, where the barrier layer is present along a bottom and a first portion of a sidewall of the at least one metal line, and the protective dielectric layer is present along a second portion of the sidewall of the at least one metal line, and where the barrier layer and the protective dielectric layer fully separate the at least one metal line from the first interlayer dielectric; depositing a second interlayer dielectric onto the first interlayer dielectric; and forming at least one conductive via in the second interlayer dielectric, where the at least one conductive via is aligned with the at least one metal line. A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional diagram illustrating a (first) interlayer dielectric having been deposited onto a wafer, and trenches having been patterned in the first interlayer dielectric according to an embodiment of the p