US-12622249-B2 - Method of manufacturing semiconductor structure including a planarization and semiconductor structure thereof

US12622249B2US 12622249 B2US12622249 B2US 12622249B2US-12622249-B2

Abstract

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

Inventors

Ying-Cheng Chuang

Assignees

NANYA TECHNOLOGY CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230821

Claims (13)

1 . A method for manufacturing a semiconductor structure, comprising: providing a substrate, including a plurality of pillars, wherein a top surface of each of the plurality of pillars is a substantially planar surface; forming a first oxide layer over the substrate conformal to the plurality of pillars, wherein each of the plurality of pillars is partially oxidized during the formation of the first oxide layer to form a rounded top surface of each of the plurality of pillars; forming a first dielectric layer over the substrate and among the pillars; partially removing each of the plurality of pillars until the rounded top surface becomes a planar top surface of the respective pillar; forming a second dielectric layer over the plurality of pillars, wherein a top surface of the second dielectric layer is a substantially planar surface; forming a plurality of first trenches in the plurality of pillars and a plurality of second trenches in the first dielectric layer between the pillars; and filling the plurality of first trenches and the plurality of second trenches with a conductive material to form a plurality of contacts; wherein a top surface of each of the plurality of contacts is below the top surface of each of the plurality of pillars.
2 . The method of claim 1 , wherein the formation of the first dielectric layer comprises: forming a first sub-layer over the first oxide layer and among the pillars; forming a second sub-layer over the first sub-layer; and removing the first sub-layer and the second sub-layer disposed above the first oxide layer.
3 . The method of claim 2 , wherein the first sub-layer and the second sub-layer include different dielectric materials.
4 . The method of claim 3 , wherein the first sub-layer include nitride and the second sub-layer includes oxide.
5 . The method of claim 2 , wherein the removal of the first sub-layer and the second sub-layer comprises: performing a polishing operation on the second sub-layer until the first sub-layer is exposed; and performing an etching operation on the first sub-layer until the first oxide layer is exposed.
6 . The method of claim 5 , wherein the polishing operation includes using a slurry with a high selectivity to the second sub-layer.
7 . The method of claim 5 , wherein the etching operation includes using an etchant with a high selectivity to the first sub-layer and a low selectivity to the second sub-layer.
8 . The method of claim 1 , wherein the first oxide layer is partially removed during the partial removal of each of the plurality of pillars.
9 . The method of claim 8 , wherein a solvent is used in the partial removal of each of the plurality of pillars, and the solvent has a high selectivity to silicon.
10 . The method of claim 8 , wherein a top surface of the first oxide layer and the top surfaces of the plurality of pillars are substantially coplanar after the partial removal of each of the plurality of pillars.
11 . The method of claim 1 , wherein the second dielectric layer includes nitride.
12 . The method of claim 1 , further comprising: forming a third dielectric layer over the plurality of contacts; and forming a fourth dielectric layer over the third dielectric layer.
13 . The method of claim 12 , wherein the third dielectric layer fills the plurality of first trenches and the plurality of second trenches above the plurality of contacts.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional application of U.S. Non-Provisional application Ser. No. 18/133,058 filed Apr. 11, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a method of manufacturing a semiconductor structure, and a semiconductor structure formed by the method. In particular, the present disclosure relates to a method including a planarization to prevent rounding from occurring due to formation of an oxide material. DISCUSSION OF THE BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment. The semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. As the semiconductor industry has progressed into advanced technology process nodes in pursuit of greater device density, higher performance, and lower costs, challenges of precise control of configuration of an element have arisen. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. SUMMARY One aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes a number of operations. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the plurality of pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the plurality of pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the plurality of pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the plurality of pillars to partially or entirely remove the convex surface. A second dielectric layer is formed over the plurality of pillars, the first oxide layer and the first dielectric layer, wherein a top surface of the second dielectric layer is a substantially planar surface. Another aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes a number of operations. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the plurality of pillars, wherein each of the plurality of pillars is partially oxidized during the formation of the first oxide layer to form a rounded top surface of each of the plurality of pillars. A first dielectric layer is formed over the substrate and among the pillars. Each of the plurality of pillars is partially removed until the rounded top surface becomes a planar top surface of the respective pillar. A second dielectric layer is formed over the plurality of pillars, wherein a top surface of the second dielectric layer is a substantially planar surface. Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The first dielectric layer surrounds each of the plurality of pillars, wherein a top surface of the first dielectric layer is substantially coplanar with the top surface of each of the plurality of pillars. The plurality of first contacts is disposed in the pillars. The plurality of second contacts is disposed between the pillars and surrounded by the first dielectric layer. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those