US-12622250-B2 - Vias with vertically non-uniform or discontinuous stack

Abstract

Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.

Inventors

• Payam Amin
• Leslie L. CHAN
• Hoang DOAN
• Dolly Natalia RUIZ AMADOR
• Tofizur RAHMAN
• Bozidar MARINKOVIC
• Santhosh Kumar KODURI
• Tugba KOKER AYKOL
• Jayeeta SEN
• David Bennett
• Conor P. Puls
• Clay Mortensen

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220331

Claims (20)

1. 1 . A via structure, comprising: a substrate; an opening through the substrate, wherein the opening has a first portion and a second portion under the first portion; a lining on sidewalls of the first portion of the opening; and a via filling the opening, wherein the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width, wherein the via has an uppermost surface at a same level as an uppermost surface of the lining, wherein the second region has a non-uniform thickness through a length of the second region of the via, and wherein an end of the second region of the via opposite from the first region of the via is rounded.
2. 2 . The via structure of claim 1 , wherein the first width is approximately ninety percent of the second width or smaller.
3. 3 . The via structure of claim 1 , wherein the first region of the via is in the first portion of the opening, and wherein the second region of the via is in the second portion of the opening.
4. 4 . The via structure of claim 1 , further comprising: a step at the junction between the first region of the via and the second region of the via.
5. 5 . The via structure of claim 4 , wherein the step is rounded.
6. 6 . The via structure of claim 1 , wherein a junction between the first region of the via and the second region of the via is tapered.
7. 7 . The via structure of claim 1 , wherein the lining comprises oxygen or nitrogen.
8. 8 . The via structure of claim 1 , wherein the via comprises tungsten.
9. 9 . The via structure of claim 1 , wherein the first region of the via has a non-uniform thickness through a length of the first region of the via.
10. 10 . The via structure of claim 1 , wherein the substrate comprises silicon.
11. 11 . A method of forming a backside via, comprising: forming an opening in a substrate, wherein the opening has a first portion and a second portion below the first portion; filling the second portion of the opening with a sacrificial material; forming a lining along sidewalls of the opening in the first portion of the opening above the sacrificial material; removing the sacrificial material; and forming a via in the opening, wherein the via has a first width at the first portion of the opening adjacent to the lining and a second width at the second portion of the opening below the lining, and wherein the via has an uppermost surface at a same level as an uppermost surface of the lining.
12. 12 . The method of claim 11 , wherein a stepped structure is provided at the junction between the first width and the second width.
13. 13 . The method of claim 12 , wherein the stepped structure is rounded.
14. 14 . The method of claim 11 , wherein a junction between the first width and the second width is tapered.
15. 15 . The method of claim 11 , wherein the first width is approximately ninety percent of the second width or smaller.
16. 16 . The method of claim 11 , wherein the lining comprises oxygen or nitrogen.
17. 17 . The method of claim 11 , wherein the via comprises tungsten.
18. 18 . The method of claim 11 , wherein filling the second portion of the opening with a sacrificial material comprises: filling the first portion of the opening and the second portion of the opening with the sacrificial material; and recessing the sacrificial material to clear the first portion of the opening.
19. 19 . A semiconductor device, comprising: a substrate; a non-planar transistor device with a source and a drain over the substrate; a via through the substrate and coupled to one of the source and the drain, wherein the via comprises: a first region with a first width, wherein the first region contacts the one of the source and the drain; and a second region with a second width below the first region, wherein the second width is greater than the first width, wherein the second region has a non-uniform thickness through a length of the second region of the via, and wherein an end of the second region of the via opposite from the first region of the via is rounded; and a lining on sidewalls of the first region of the via, wherein the via has an uppermost surface at a same level as an uppermost surface of the lining.
20. 20 . The semiconductor device of claim 19 , wherein a junction between the first region and the second region is a stepped interface.

Description

TECHNICAL FIELD Embodiments of the disclosure are in the field of semiconductor structures and processing and, in particular, to backside contact architectures for non-planar transistor structures. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. Variability in conventional and currently known fabrication processes may limit the possibility to further extend them into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors and gate-all-around (GAA) transistors, have become more prevalent as device dimensions continue to scale down. Tri-gate transistors and GAA transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional illustration of a backside via with a first region with a first width and a second region with a second width, in accordance with an embodiment. FIG. 1B is a cross-sectional illustration of a backside via with a first region with a first width and a second region with a second width and a rounded bottom surface, in accordance with an embodiment. FIG. 2A is a zoomed in cross-sectional illustration highlighting a square stepped interface between the first region of the backside via and the second region of the backside via, in accordance with an embodiment. FIG. 2B is a zoomed in cross-sectional illustration highlighting a rounded stepped interface between the first region of the backside via and the second region of the backside via, in accordance with an embodiment. FIG. 2C is a zoomed in cross-sectional illustration highlighting a tapered interface between the first region of the backside via and the second region of the backside via, in accordance with an embodiment. FIG. 2D is a zoomed in cross-sectional illustration highlighting a rounded tapered interface between the first region of the backside via and the second region of the backside via, in accordance with an embodiment. FIG. 3A is a cross-sectional illustration of a substrate, in accordance with an embodiment. FIG. 3B is a cross-sectional illustration of the substrate after a backside via opening is formed through a thickness of the substrate, in accordance with an embodiment. FIG. 3C is a cross-sectional illustration of the substrate after a sacrificial material is disposed into the opening, in accordance with an embodiment. FIG. 3D is a cross-sectional illustration of the substrate after the sacrificial material is recessed, in accordance with an embodiment. FIG. 3E is a cross-sectional illustration of the substrate after a liner is deposited into the opening, in accordance with an embodiment. FIG. 3F is a cross-sectional illustration of the substrate after the bottom of the liner is removed to expose the sacrificial material, in accordance with an embodiment. FIG. 3G is a cross-sectional illustration of the substrate after the sacrificial material is removed, in accordance with an embodiment. FIG. 3H is a cross-sectional illustration of the substrate after a via is deposited in the opening, in accordance with an embodiment. FIG. 4A is a cross-sectional illustration of a tri-gate transistor with a backside via to a source/drain region, in accordance with an embodiment. FIG. 4B is a cross-sectional illustration of a gate-all-around (GAA) transistor with a backside via to a source/drain region, in accordance with an embodiment. FIG. 5 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure. FIG. 6