US-12622251-B2 - Via connection structure having multiple via to via connections

US12622251B2US 12622251 B2US12622251 B2US 12622251B2US-12622251-B2

Abstract

Connection structures and methods of manufacture in which a conductive structure is disposed between, and in electrical contact with, pluralities of via structures. Each via structure is laterally offset from adjacent via structures to avoid stacked vias, and each via is electrically connected to at least two additional vias on a level of a semiconductor device, through conductive traces and footprints of the connection structure.

Inventors

Ting-Yu Yeh
Shu-Cheng Li
Chun-Hsien Wen
Chih-Wei Chang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20220526

Claims (18)

1 . A semiconductor device, comprising: a first conductive structure comprising: a first plurality of conductive traces impregnated along a first shared plane of a first level of a connection structure; a second plurality of conductive traces impregnated along a second shared plane of a second level of the connection structure; a plurality of first via structures disposed below and in electrical contact with the first level of the first conductive structure; and a plurality of second via structures disposed above and in electrical contact with the first level of the first conductive structure; wherein: each of the plurality of first via structures is laterally offset from any portion of any of the plurality of second via structures, two of the first plurality of conductive traces connect each of the plurality of first via structures to two of the plurality of second via structures, the plurality of second via structures extend between the first level and the second level; and the plurality of first via structures and the plurality of second via structures are arranged in hexagonal patterns, wherein an innermost one of the hexagonal patterns laterally surrounds an innermost one via structure and has six via structures, and wherein each hexagonal pattern has a difference of six via structures from any concentrically adjacent hexagonal pattern.
2 . The semiconductor device of claim 1 , wherein a number of concentric hexagonal patterns surrounding the innermost one via structure is three.
3 . The semiconductor device of claim 1 , wherein each of the concentric hexagonal patterns, has at least a first footprint for a corresponding one of the plurality of first via structures and at least a second footprint for a corresponding one of the plurality of second via structures.
4 . The semiconductor device of claim 3 , wherein at least the first footprint and at least the second footprint are laterally next to each other.
5 . The semiconductor device of claim 1 , wherein the connection structure is impregnated in a polymer body.
6 . The semiconductor device of claim 5 , wherein the polymer body comprises a high-k dielectric.
7 . The semiconductor device of claim 1 , further comprising: a third plurality of conductive traces impregnated in a third shared plane of a third level of the connection structure; and a plurality of third via structures disposed above and in electrical contact with the second level of the first conductive structure, wherein the plurality of second via structures extend between the second level and the third level.
8 . The semiconductor device of claim 1 , further comprising: a third conductive structure impregnated in the first level of the connection structure; and a fourth conductive structure impregnated m the first level of the connection structure, wherein: the first conductive structure Is configured to deliver a first supply voltage, while the third and fourth conductive structures are configured to deliver a second supply voltage, and the first conductive structure includes a bridge portion extending between the third and fourth conductive structures.
9 . The semiconductor device of claim 8 , further comprising a plurality of third via structures disposed within the bridge portion.
10 . A connection structure, comprising: a plurality of first via structures arranged in one or more first ones of a plurality of concentric hexagonal patterns; a plurality of second via structures arranged in one or more second ones of the plurality of concentric hexagonal patterns; and a first conductive structure, comprising a plurality of conductive traces disposed along a shared plane, interposed between and in electrical contact with the plurality of first via structures and the second plurality of second via structures; and wherein: each of the plurality of first via structures is laterally offset from any portion of the plurality of second via structure, and the plurality of conductive traces along the shared plane electrically couple each of the first via structures to two of the second via structures, and each of the second via structures to two of the first via structures.
11 . The connection structure of claim 10 wherein the plurality of concentric hexagonal patterns comprise: the first via structures at a first subset of footprints comprising vertices of the hexagons; and a second subset of via structures at a second subset of the footprints, complementary to the first subset.
12 . The connection structure of claim 10 wherein each of the plurality of first via structures has a respective connection path to each of two of the plurality of second via structures.
13 . The connection structure of claim 10 wherein the first conductive structure, the plurality of first via structures, and the plurality of second via structures form, at least in part, a power delivery network.
14 . The connection structure of claim 10 wherein the connection structure is disposed within a dielectric body comprising a polymer.
15 . A semiconductor device, comprising: a connection structure comprising: a first conductive structure comprising a first plurality of conductive traces impregnated along a same plane of a first level; a plurality of first via structures disposed below and in electrical contact with the first conductive structure; and a plurality of second via structures disposed above and in electrical contact with the first conductive structure and extending to a second level of the conductive structure comprising a second plurality of conductive traces electrically coupling the second via structures with third via structures; wherein each of the plurality of first via structures is laterally offset from any portion of any of the plurality of second via structures, and two of the first plurality of conductive traces connect each of the plurality of first via structures to two of the plurality of second via structures; a plurality of semiconductor chips connected to a first side of the connection structure; and a plurality of bump structures on a second, opposite side of the connection structure, wherein the plurality of first via structures and the plurality of second via structures are arranged in hexagonal patterns, wherein an innermost one of the hexagonal patterns laterally surrounds an innermost one via structure and has six via structures, and wherein each hexagonal pattern has a difference of six via structures from any concentrically adjacent hexagonal pattern.
16 . The semiconductor device of claim 15 , wherein a number of concentric hexagonal patterns is three.
17 . The semiconductor device of claim 15 , further comprising a dielectric encapsulating a plurality of the first or the second via structures.
18 . The semiconductor device of claim 15 , wherein the connection structure further comprises a second conductive structure impregnated in a second level of the semiconductor device, disposed between the first conductive structure and the bumps, electrically connected to the first conductive structure through at least one of the plurality of first via structures or the plurality of second via structures, and connected to the bumps through a plurality of third via structures.

Description

BACKGROUND Semiconductor devices are ubiquitous in several applications and devices throughout various industries. For example, consumer electronics devices such as personal computers, cellular telephones, and wearable devices may contain several semiconductor devices. Similarly, industrial products such as instruments, vehicles, and automation systems frequently comprise a large number of semiconductor devices. As semiconductor manufacturing improves, semiconductors continue to be used in new applications which, in turn, leads to increasing demands of semiconductor performance, cost, reliability, etc. These semiconductor devices are fabricated by a combination of front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes, which connect one or more semiconductor (e.g., silicon) dies to each other and package them into a semiconductor device that can interface with other devices. For example, the package may combine a plurality of semiconductor dies and can be configured to be attached to a printed circuit board or other interconnected substrate, which may, in turn, increase the thermal and connection density of a semiconductor device. Many BEOL operations comprise processing a semiconductor or related device by alternatively depositing and etching levels of the device, one disposed over the other. Processes may interconnect levels by a redistribution structures, vias, bonding wires, etc. in order to propagate signals within a semiconductor device, and between a semiconductor device and a substrate, connections (e.g., electrical, thermal, mechanical, etc.) are formed between levels of semiconductor devices. While existing approaches use sophisticated techniques, further improvements are needed to advance the state of the art. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a hexagonal via structure, in accordance with some embodiments. FIGS. 2a, 2b, 2c, and 2d illustrate a plurality of patterns for a concentric hexagonal connection structure having two concentric hexagons, in accordance with some embodiments. FIG. 3 illustrates a selection matrix for patterns of various numbers of concentric hexagons. FIGS. 4a, 4b, 4c, 4d, 4e, and 4f illustrate a plurality of patterns for a concentric hexagonal connection structure having three concentric hexagons, in accordance with some embodiments. FIGS. 5a, 5b, 5c, 5d, 5e, 5f, 5g, and 5h illustrate a plurality of patterns for a concentric hexagonal connection structure having four concentric hexagons, in accordance with some embodiments. FIG. 6 illustrates a pair of laterally disposed patterns for a concentric hexagonal connection structures having four concentric hexagons. FIGS. 7a, 7b, 7c, 7d, 7e, and 7f illustrate cross sectional views of intermediate stages in the formation of a connection structure, in accordance with some embodiments. FIG. 8 includes a flowchart of an example method of fabricating a semiconductor device, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Disclosed herein are laterally offset (e.g., n