US-12622252-B2 - Backside contacts for source/drain regions

Abstract

A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Inventors

• Albert M. Chu
• Junli Wang
• Brent A. Anderson
• Leon Sigal
• David Wolpert
• Ruilong Xie
• Jay William Strane

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20230501

Claims (18)

1. 1 . A semiconductor structure comprising: a first transistor, wherein the first transistor comprises a first input source/drain region and a first output source/drain region; a second transistor, wherein the second transistor comprises a second input source/drain region and a second output source/drain region; a first source/drain contact commonly connected to the first input source/drain region and the second input source/drain region; a second source/drain contact commonly connected to the first output source/drain region and the second output source/drain region; a third source/drain contact connecting the first input source/drain region and the second input source/drain region to a first power rail; and a fourth source/drain contact connecting the first output source/drain region and the second output source/drain region to second power rail; wherein the first source/drain contact and the second source/drain contact are on a first side of the semiconductor structure; and wherein the third source/drain contact and the fourth source/drain contact are on a second side of the semiconductor structure, opposite the first side.
2. 2 . The semiconductor structure of claim 1 , wherein: the first side of the semiconductor structure comprises a frontside of the semiconductor structure; and the second side of the semiconductor structure comprises a backside of the semiconductor structure.
3. 3 . The semiconductor structure of claim 2 , wherein at least one edge of the first source/drain contact is self-aligned with at least one edge of the first input source/drain region.
4. 4 . The semiconductor structure of claim 3 , wherein at least one edge of the second source/drain contact is self-aligned with at least one edge of the second output source/drain region.
5. 5 . The semiconductor structure of claim 1 , further comprising at least one gate structure common to the first transistor and the second transistor.
6. 6 . The semiconductor structure of claim 1 , wherein the first transistor and the second transistor have a same doping type.
7. 7 . The semiconductor structure of claim 6 , further comprising a third transistor adjacent the second transistor, wherein the third transistor has a different doping type than that of the first transistor and the second transistor.
8. 8 . The semiconductor structure of claim 1 , wherein the first transistor and the second transistor are nanosheet transistors.
9. 9 . A semiconductor structure comprising: a plurality of input source/drain regions connected to a first wire through a first contact; and a plurality of output source/drain regions connected to a second wire through a second contact; wherein the first wire and the second wire are on a same side of the semiconductor structure; and wherein the plurality of input source/drain regions and the plurality of output source/drain regions correspond to a merged transistor, wherein the merged transistor comprises a first transistor and a second transistor.
10. 10 . The semiconductor structure of claim 9 , wherein the same side of the semiconductor structure comprises a backside of the first transistor and of the second transistor.
11. 11 . The semiconductor structure of claim 9 , further comprising a third transistor adjacent the merged transistor and at least one gate structure common to the merged transistor and the third transistor, wherein: the first transistor and the second transistor have a same doping type; and the third transistor has a different doping type than that of the first transistor and the second transistor.
12. 12 . The semiconductor structure of claim 9 , wherein the first transistor and the second transistor are nanosheet transistors.
13. 13 . The semiconductor structure of claim 9 , wherein: the first wire comprises a first power rail; and the second wire comprises a second power rail.
14. 14 . A semiconductor structure comprising: a plurality of transistors comprising a first transistor, a second transistor adjacent the first transistor and a third transistor adjacent the second transistor, wherein the first transistor and the second transistor have a same doping type, and the third transistor has a different doping type than that of the first transistor and the second transistor; at least one gate structure common to the first transistor, the second transistor and the third transistor; a first input source/drain region and a first output source/drain region corresponding to the first transistor; and a second input source/drain region and a second output source/drain region corresponding to the second transistor; wherein the first input source/drain region and the second input source/drain region are connected to a first source/drain contact; and wherein the first output source/drain region and the second output source/drain region are connected to a second source/drain contact.
15. 15 . The semiconductor structure of claim 14 , wherein: at least one edge of the first source/drain contact is self-aligned with at least one edge of the first input source/drain region; and at least one edge of the second source/drain contact is self-aligned with at least one edge of the second output source/drain region.
16. 16 . The semiconductor structure of claim 14 , wherein the first source/drain contact and the second source/drain contact are disposed on a backside of the plurality of transistors and are respectively connected to a first wire and a second wire disposed on the backside of the plurality of transistors.
17. 17 . The semiconductor structure of claim 16 , wherein the first wire contacts the first source/drain contact, and the second wire contacts the second source/drain contact.
18. 18 . The semiconductor structure of claim 14 , wherein the plurality of transistors comprises a plurality of nanosheet transistors.

Description

BACKGROUND The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors. A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, and having action that depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFET and pFET) are used to fabricate logic and other circuitry. Source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with the gate being formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage current from flowing into the channel when voltage is applied to the gate conductor while allowing applied gate voltage to produce a transverse electric field in the channel. Various techniques may be used to reduce the size of FETs. One technique is through the use of fin-shaped channels in FinFET devices. Before the advent of FinFET arrangements, CMOS devices were typically substantially planar along the surface of the semiconductor substrate, with the exception of the FET gate disposed over the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in FinFET structures the gate can more effectively control the channel, as the gate extends over more than one side or surface of the channel. In some FinFET arrangements, the gate encloses three surfaces of the three-dimensional channel, rather than being disposed over just the top surface of a traditional planar channel. Another technique useful for reducing the size of FETs is through the use of stacked nanosheet channels formed over a semiconductor substrate. Stacked nanosheets may be two-dimensional nanostructures, such as sheets having a thickness range on the order of 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7 nm and beyond. A general process flow for formation of a nanosheet stack involves removing sacrificial layers, which may be formed of silicon germanium (SiGe), between sheets of channel material, which may be formed of silicon (Si). With conventional approaches, connections to source/drain regions of FETs from backside power rails are typically made by through vias from the backside to the frontside of a semiconductor device. As a result, the semiconductor manufacturing processes are undesirably complex. In addition, the resulting structures impede size reductions and further miniaturization due to the need to accommodate the through vias. SUMMARY Embodiments of the invention provide techniques for forming efficient connections to backside power sources by using direct backside contacts. In one embodiment, a semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on the same side of the semiconductor structure. As may be combined with the preceding paragraph, the same side of the semiconductor structure may comprise the backside of the semiconductor structure. The first source/drain contact and the second source/drain contact may be respectively connected to a first wire and a second wire disposed on the backside of the semiconductor structure. At least one edge of the first source/drain contact may be self-aligned with at least one edge of the first input source/drain region, and at least one edge of the second sou