US-12622255-B2 - Integrated circuit structures with pre-epitaxial deep via structure

Abstract

Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

Inventors

• Leonard P. GULER
• Sukru Yemenicioglu
• Makram ABD EL QADER
• Tahir Ghani
• Chanaka D. Munasinghe

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220331

Claims (9)

1. 1 . An integrated circuit structure, comprising: a plurality of horizontally stacked nanowires; a gate structure over the plurality of horizontally stacked nanowires; an epitaxial source or drain structure at an end of the plurality of horizontally stacked nanowires; a conductive trench contact structure vertically over the epitaxial source or drain structure; a conductive via vertically beneath and extending into the conductive trench contact structure, the conductive via having an uppermost surface above an uppermost surface of the epitaxial source or drain structure; and a dielectric liner laterally around the conductive via, wherein a portion of the dielectric liner laterally between the conductive via and the epitaxial source or drain structure has a top surface below the uppermost surface of the epitaxial source or drain structure.
2. 2 . The integrated circuit structure of claim 1 , wherein the conductive via and the conductive trench contact structure have a same composition.
3. 3 . The integrated circuit structure of claim 1 , wherein the conductive via and the conductive trench contact structure have a different composition.
4. 4 . The integrated circuit structure of claim 1 , further comprising a dielectric plug over the conductive via.
5. 5 . A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a plurality of horizontally stacked nanowires; a gate structure over the plurality of horizontally stacked nanowires; an epitaxial source or drain structure at an end of the plurality of horizontally stacked nanowires; a conductive trench contact structure vertically over the epitaxial source or drain structure; a conductive via vertically beneath and extending into the conductive trench contact structure, the conductive via having an uppermost surface above an uppermost surface of the epitaxial source or drain structure; and a dielectric liner laterally around the conductive via, wherein a portion of the dielectric liner laterally between the conductive via and the epitaxial source or drain structure has a top surface below the uppermost surface of the epitaxial source or drain structure.
6. 6 . The computing device of claim 5 , further comprising: a memory coupled to the board.
7. 7 . The computing device of claim 5 , further comprising: a communication chip coupled to the board.
8. 8 . The computing device of claim 5 , wherein the component is a packaged integrated circuit die.
9. 9 . The computing device of claim 5 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1G illustrate cross-sectional views representing various operations in methods of fabricating an integrated circuit structure having a pre-epitaxial deep via structure, in accordance with an embodiment of the present disclosure. FIGS. 2A-2E illustrate angled cross-sectional views representing various operations in methods of fabricating an integrated circuit structure having a trench contact flyover structure and a pre-epitaxial deep via structure, in accordance with an embodiment of the present disclosure. FIG. 3 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. FIGS. 4A-4H illustrate plan views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. FIGS. 5A-5H illustrate cross-sectional views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. FIG. 6 illustrates a cross-sectional view taken through nanowires and fins for a non-endcap architecture, in accordance with an embodiment of the present disclosure. FIG. 7 illustrates a cross-sectional view taken through nanowires and fins for a self-aligned gate endcap (SAGE) architecture, in accordance with an embodiment of the present disclosure. FIG. 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of FIG. 8A, as taken along the a-a′ axis, in accordance with an embodiment of the present disclosure. FIG. 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 8A, as taken along the b-b′ axis, in accordance with an embodiment of the present disclosure. FIG. 9 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure. FIG. 10 illustrates an interposer that includes one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design