US-12622256-B2 - Conductive via structures for far-end crosstalk cancellation

Abstract

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

Inventors

• Yanbin Chen
• Tengfei Wang
• TINGTING PANG
• Shuai Wang
• Huili Fu
• Wenkai FAN
• Xu Yan
• Huan Liu
• Jianwei Guo

Assignees

• T-Head (Shanghai) Semiconductor Co., Ltd.

Dates

Publication Date

20260505

Application Date

20220812

Priority Date

20220311

Claims (20)

1. 1 . A semiconductor structure, comprising: a substrate, comprising a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the plurality of conductive layers to a bottom conductive layer of the plurality of conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the plurality of conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the plurality of conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure, wherein the plurality of insulating layers comprise a top insulating layer and a bottom insulating layer, wherein each of the first conductive via structure and the second conductive via structure extends through the top insulating layer and the bottom insulating layer, wherein the third capacitive structure is fully encapsulated by the insulating layers and is free from being electrically connected to any conductive element extending through the top insulating layer or the bottom insulating layer.
2. 2 . The semiconductor structure of claim 1 , wherein the first capacitive structure and the second capacitive structure do not overlap in projection in the vertical direction.
3. 3 . The semiconductor structure of claim 1 , wherein the third capacitive structure is overlapped in projection with the first capacitive structure and the second capacitive structure in the vertical direction.
4. 4 . The semiconductor structure of claim 1 , wherein the third capacitive structure is symmetric about a central line of the third capacitive structure from a cross-sectional view.
5. 5 . The semiconductor structure of claim 1 , wherein the first conductive layer is arranged in the top conductive layer or another conductive layer between the top conductive layer and the bottom conductive layer.
6. 6 . The semiconductor structure of claim 1 , wherein the third capacitive structure comprises a first conductive pad arranged in a conductive layer same as the first capacitive structure and the second capacitive structure.
7. 7 . The semiconductor structure of claim 6 , wherein the first capacitive structure comprises a second conductive pad, the first conductive via structure further comprises a third conductive pad arranged in a third conductive layer of the plurality of conductive layers, wherein an area of the second conductive pad is greater than an area of the third conductive pad.
8. 8 . The semiconductor structure of claim 7 , wherein the first conductive via structure further comprises a fourth conductive pad arranged in the third conductive layer, wherein the third conductive pad and the fourth conductive pad are connected through a connecting portion, and wherein the third capacitive structure and the fourth conductive pad form a third mutual capacitance.
9. 9 . The semiconductor structure of claim 8 , wherein the second conductive via structure further comprises a fifth conductive pad arranged in the third conductive layer, wherein the third capacitive structure forms a fourth mutual capacitance with the fifth conductive pad.
10. 10 . The semiconductor structure of claim 9 , wherein the fourth conductive pad and the fifth conductive pad do not overlap in projection in the vertical direction.
11. 11 . The semiconductor structure of claim 1 , wherein the third capacitive structure and the first capacitive structure or the second capacitive structure do not overlap in projection in the vertical direction.
12. 12 . The semiconductor structure of claim 1 , wherein the third capacitive structure forms the first mutual capacitance with the first capacitive structure arranged in the first conductive layer and the second mutual capacitance with the second capacitive structure arranged in the first conductive layer.
13. 13 . The semiconductor structure of claim 1 , further comprising a fourth capacitive structure, wherein the third capacitive structure and the fourth capacitive structure are arranged in different layers of the plurality of conductive layers, wherein the fourth capacitive structure forms a fifth mutual capacitance with the first conductive via structure and forms a sixth mutual capacitance with the second conductive via structure.
14. 14 . The semiconductor structure of claim 13 , wherein the third capacitive structure is electrically insulated from the fourth capacitive structure.
15. 15 . The semiconductor structure of claim 13 , wherein the third capacitive structure and the fourth capacitive structure overlap in projection, partially overlap in projection, or do no overlap in projection in the vertical direction.
16. 16 . The semiconductor structure of claim 13 , wherein the first via structure comprises a sixth conductive pad, wherein the fourth capacitive structure and the sixth conductive pad are arranged in a same conductive layer of the plurality of conductive layers, wherein the fourth capacitive structure and the sixth conductive pad form a seventh mutual capacitance.
17. 17 . An electronic device, comprising: the semiconductor structure according to claim 1 ; a printed circuit board arranged on a first side of the semiconductor structure and adjacent to the bottom conductive layer of the semiconductor structure; a connector between the printed circuit board and the semiconductor structure; and a chip on a second side of the semiconductor structure opposite the first side and adjacent to the top conductive layer of the semiconductor structure, wherein the printed circuit board is electrically connected to the chip through the connector and the first conductive via structure and the second conductive via structure of the semiconductor structure.
18. 18 . A method of crosstalk cancellation, comprising: transmitting an electrical signal in a first conductive via structure and a second conductive via structure of a semiconductor structure, the first conductive via structure including a first capacitive structure and a second capacitive structure, wherein the semiconductor structure further comprises a third capacitive structure separate from the first conductive via structure and the second conductive via structure; and during the transmitting of the electrical signal in the first conductive via structure and the second conductive via structure, storing energy in an electric field through a first mutual capacitance between the first capacitive structure and the third capacitive structure and a second mutual capacitance between the second capacitive structure and the third capacitive structure, wherein the semiconductor structure comprises a plurality of insulating layers stacked alternately with each other along a vertical direction, wherein the plurality of insulating layers comprise a top insulating layer and a bottom insulating layer, wherein each of the first conductive via structure and the second conductive via structure extends through the top insulating layer and the bottom insulating layer, wherein the third capacitive structure is fully encapsulated by the insulating layers and is free from being electrically connected to any conductive element extending through the top insulating layer or the bottom insulating layer.
19. 19 . The method of claim 18 , wherein the first capacitive structure and the second capacitive structure extend in a vertical direction, wherein the first capacitive structure and the second capacitive structure do not overlap in projection in the vertical direction, wherein the third capacitive structure includes a first portion overlapped in projection with and the first capacitive structure in the vertical direction, and wherein the third capacitive structure includes a second portion overlapped in projection with the second capacitive structure in the vertical direction.
20. 20 . The method of claim 18 , wherein the first capacitive structure of the first conductive via structure or the second capacitive structure of the second conductive via structure comprises a conductive pad in a top conductive layer or a bottom conductive layer of a plurality of conductive layers of the semiconductor structure.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims priority to Chinese Pat. Application No. 202210245727.0 filed Mar. 11, 2022, the disclosures of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor structure, and more particularly to a conductive via structure for improving crosstalk in the semiconductor structure. BACKGROUND The transmission performance required by the advanced signaling system includes faster transmission speed and smaller chip size to achieve better user experience. However, in a high-speed signal transmission system, due to increased routing density and increased signal transmission frequency, the crosstalk induced between adjacent signal transmission paths continues to be a challenging task. For example, far-end crosstalk (FEXT) between transmission paths has become a major problem to be solved to mitigate the crosstalk effect. Accordingly, efforts have been developed in the field in enhancing the transmission architectures and methods for reducing or eliminating the FEXT. SUMMARY According to an embodiment of the present disclosure, a semiconductor structure includes: a substrate, including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the plurality of conductive layers to a bottom conductive layer of the plurality of conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the plurality of conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the plurality of conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure. In an embodiment, the first capacitive structure and the second capacitive structure do not overlap in projection in the vertical direction. In an embodiment, the third capacitive structure is overlapped in projection with the first capacitive structure and the second capacitive structure in the vertical direction. In an embodiment, the first conductive layer is arranged in the bottom conductive layer. In an embodiment, the first conductive layer is arranged in the top conductive layer or another conductive layer between the top conductive layer and the bottom conductive layer. In an embodiment, the third capacitive structure includes a first conductive pad arranged in a conductive layer same as the first capacitive structure and the second capacitive structure. In an embodiment, the first capacitive structure includes a second conductive pad, the first conductive via structure further includes a third conductive pad arranged in a third conductive layer of the plurality of conductive layers, wherein an area of the second conductive pad is greater than an area of the third conductive pad. In an embodiment, the first conductive via structure further includes a fourth conductive pad arranged in the third conductive layer, wherein the third conductive pad and the fourth conductive pad are connected through a connecting portion, and wherein the third capacitive structure and the fourth conductive pad form a third mutual capacitance. In an embodiment, the second conductive via structure further includes a fifth conductive pad arranged in the third conductive layer, wherein the third capacitive structure forms a fourth mutual capacitance with the fifth conductive pad. In an embodiment, the fourth conductive pad and the fifth conductive pad do not overlap in projection in the vertical direction. In an embodiment, the third capacitive structure and the first capacitive structure or the second capacitive structure do not overlap in projection in the vertical direction. In an embodiment, the semiconductor structure further includes a third conductive via structure, separate from the first conductive via structure and the second conductive via structure, and extending to a fourth conductive layer of the plurality of conductive layers from the second conductive layer, wherein the third capacitive structure is included in the third conductive via structure. In an embodiment, the semiconductor structure further includes a fourth capacitive structure, wherein the third capacitive structure and the fourth capacitive structure are arranged in different layers of the plurality of conductive layers, wherein the fourth capacitive structure forms a fifth mutual capacitance with the first conductive via structure and forms a sixth mutual capacitance with the second condu