US-12622258-B2 - Self-aligned staggered integrated circuit interconnect features

Abstract

Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Inventors

• Miriam Reshotko
• Elijah Karpov
• Mark Anders
• Gauri Auluck
• Shakuntala Sundararajan
• Michael MAKOWSKI
• Caleb Barrett

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220606

Claims (20)

1. 1 . An integrated circuit (IC) interconnect structure, comprising: a plurality of first interconnect lines with spaces therebetween; a dielectric material over the first interconnect lines and within the spaces, wherein topography of the dielectric material comprises a plurality of trenches between the first interconnect lines; and a plurality of second interconnect lines interdigitated with the first interconnect lines, wherein the second interconnect lines occupy at least a portion of the trenches between individual ones of the first interconnect lines, and wherein bottoms of the second interconnect lines are vertically offset above bottoms of the first interconnect lines by at least a first thickness of the dielectric material that is greater than a second thickness of the dielectric material between nearest edges of adjacent ones of the first and second interconnect lines.
2. 2 . The IC interconnect structure of claim 1 , wherein: the first interconnect lines are within a first plane of the structure; and the second interconnect lines are within a second plane of the structure.
3. 3 . The IC interconnect structure of claim 2 , further comprising a plurality of third interconnect lines within a third plane of the structure, wherein the third interconnect lines extend in a first direction substantially orthogonal to a second direction of the first and second interconnect lines.
4. 4 . The IC interconnect structure of claim 2 , wherein the second plane is above the first plane.
5. 5 . The IC interconnect structure of claim 1 , wherein the first thickness is at least 1.5 times the second thickness.
6. 6 . The IC interconnect structure of claim 1 , wherein a first ridge of the dielectric material over one of the first interconnect lines is substantially planar with a second ridge of the dielectric material over another of the first interconnect lines.
7. 7 . The IC interconnect structure of claim 6 , wherein the second interconnect lines substantially fill the trenches and a top surface of one of the second interconnect lines between the first and second ridges is substantially planar with a top surface of the first and second ridges.
8. 8 . The IC interconnect structure of claim 6 , wherein the second interconnect lines occupy only a bottom portion of the trenches and a top surface of one of the second interconnect lines between the first and second ridges is below a top surface of the first and second ridges.
9. 9 . The IC interconnect structure of claim 1 , wherein the first interconnect lines have line pitch, and wherein the first thickness is more than half of the line pitch.
10. 10 . The IC interconnect structure of claim 1 , wherein the first and second interconnect lines have different chemical compositions.
11. 11 . The IC interconnect structure of claim 1 , wherein the first and second interconnect lines have substantially the same chemical composition.
12. 12 . The IC interconnect structure of claim 1 , wherein a first of the first or second interconnect lines comprise Cu.
13. 13 . The IC interconnect structure of claim 12 , wherein a second of the first or second interconnect lines comprise predominantly W, Ru, Mo, or Co.
14. 14 . The IC interconnect structure of claim 1 , wherein the dielectric material comprises a first material layer in contact with the first interconnect lines, and a second material layer on the first material layer, and wherein the first material layer comprises silicon and nitrogen.
15. 15 . The IC interconnect structure of claim 1 , further comprising a plurality of interconnect vias within a third plane of the structure, over the second plane, wherein a first of the interconnect vias intersects one of the first interconnect lines and wherein a second of the interconnect vias intersects one of the second interconnect lines.
16. 16 . An integrated circuit (IC) structure, comprising: a device layer comprising a plurality of transistors or memory cells; and an interconnect structure electrically coupled the device layer, wherein the interconnect structure further comprises: a plurality of first interconnect lines with spaces therebetween; a dielectric material over the first interconnect lines and within the spaces, wherein topography in the dielectric material defines a plurality of trenches between the first interconnect lines; and a plurality of second interconnect lines interdigitated with the first interconnect lines, wherein the second interconnect lines occupy at least a portion of each of the trenches between individual ones of the first interconnect lines, comprise predominantly W, Ru, Mo, or Co, and wherein a top surface of a first length of the one of the second interconnect lines is below a top surface of a second length of the one of the second interconnect lines.
17. 17 . The IC structure of claim 16 , wherein the top surface of the first length is below a top surface of a length of one or more of the first interconnect lines.
18. 18 . A method of fabricating an interconnect structure, the method comprising: forming first interconnect lines; forming trenches staggered from the first interconnect lines by super-conformally depositing a non-planar dielectric material layer over the first interconnect lines and within spaces therebetween; depositing metallization over a non-planar surface of the dielectric material layer; and forming parallel second interconnect lines by planarizing the metallization within the trenches with ridges of the non-planar dielectric material layer between the trenches, wherein bottoms of the second interconnect lines are vertically offset above bottoms of the first interconnect lines by a first thickness of the dielectric material that is greater than a second thickness of the dielectric material between nearest edges of adjacent ones of the first and second interconnect line.
19. 19 . The method of claim 18 , wherein the first interconnect lines are over a substrate material, and the method further comprises increasing a depth of the trenches by recess etching the substrate material between the first interconnect lines.
20. 20 . The method of claim 18 , wherein forming the second interconnect lines further comprises recess etching the second interconnect lines after planarizing the metallization.

Description

BACKGROUND Demand for higher performance integrated circuits (ICs) in electronic device applications has motivated increasingly dense transistor architectures. Interconnect parasitics become a greater challenge as the density of interconnect metallization structures keeps pace with transistor density. For example, the resistance-capacitance (RC) delay associated with interconnects of an IC increase with the density of the interconnects. Large energy delay products attributable to line-to-line capacitance leads to higher power consumption and degraded performance. Low-k interlevel dielectric materials and air gap solutions have been enlisted to lower interconnect capacitance. However, low-K ILDs are difficult to pattern and often do not maintain their low relative permittivity characteristics after typical fabrication processes, making such materials hard to integrate into high volume manufacturing. Air gap solutions often require extra patterning processes, which can significantly increase manufacturing cost. The implementation of air gaps can also compromise mechanical stability of an IC device. Accordingly, interconnect structures, and techniques for fabricating such structures, with reduced capacitive coupling between nearest interconnect lines of a given lateral line pitch would be commercially advantageous over alternative techniques and structures. BRIEF DESCRIPTION OF THE DRAWINGS The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. Although the figures may illustrate embodiments where structures are substantially aligned to Cartesian axes (e.g., device structures having substantially vertical sidewalls), positive and negative (re-entrant) sloped feature sidewalls often occur in practice. For example, manufacturing non-idealities may cause one or more structural features to have sloped sidewalls. Thus, attributes illustrated are idealized merely for the sake of clearly describing salient features. In the figures: FIG. 1 is a flow diagram illustrating self-aligned methods of fabricating an IC having self-aligned staggered interconnect features, in accordance with some embodiments; FIGS. 2, 3, 4, 5, 6, 7, 8 and 9 illustrate cross-sectional isometric views of an IC interconnect structure including self-aligned staggered interconnect lines evolving as operations in the methods depicted in FIG. 1 are practiced, in accordance with some exemplary embodiments; FIGS. 10, 11A, 11B and 11C illustrate cross-sectional isometric views of an IC interconnect structure having self-aligned staggered interconnect lines, in accordance with some alternative embodiments; FIG. 12 illustrates a mobile computing platform and a data server machine employing an IC with embedded memory including self-aligned staggered interconnect lines, in accordance with some embodiments; and FIG. 13 is a functional block diagram of an electronic computing device, in accordance with some embodiments. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, this is for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents. In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments