US-12622259-B2 - Method for fabricating semiconductor structure, and semiconductor structure

US12622259B2US 12622259 B2US12622259 B2US 12622259B2US-12622259-B2

Abstract

Embodiments are a method for fabricating a semiconductor structure. The method includes: providing a substrate; etching the substrate to form bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer to obtain a bit line structure; etching to form a substrate of the bit line structure, and to obtain a plurality of active area structures arranged at intervals and a first groove, the bit line structure intersecting with the active area structures; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the word line groove.

Inventors

Jingwen Lu

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230803
Priority Date: 20210827

Claims (14)

1 . A method for fabricating a semiconductor structure comprising: providing a substrate; etching the substrate to form, in the substrate, a plurality of bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer in each of the plurality of bit line grooves to obtain a bit line structure; etching the substrate in which the bit line structure is formed to obtain a plurality of active area structures arranged at intervals and a first groove, wherein the bit line structure intersects with the plurality of active area structures, respectively; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form, in the first structure, a plurality of word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in each of the plurality of word line grooves.
2 . The method according to claim 1 , wherein the first isolation layer comprises a first sub isolation layer and a second sub isolation layer; and the sequentially forming the first isolation layer, the bit line metal line layer, the bit line conductive connection layer and the first insulating layer in each of the plurality of bit line grooves to obtain the bit line structure comprises: depositing the first sub isolation layer on a bottom of each of the plurality of bit line grooves; depositing a second sub isolation layer on the bottom and a side wall of each of the plurality of bit line grooves where the first sub isolation layer is formed; depositing a barrier layer on the bottom and the side wall of each of the plurality of bit line grooves where the second sub isolation layer is formed; depositing a bit line metal line material layer in each of the plurality of bit line grooves where the barrier layer is formed; etching back the barrier layer and the bit line metal line material layer to obtain the bit line metal line layer; depositing the bit line conductive connection layer in each of the plurality of bit line grooves where the bit line metal line layer is formed; and depositing the first insulating layer in each of the plurality of bit line grooves where the bit line conductive connection layer is formed to obtain the bit line structure.
3 . The method according to claim 1 , wherein each of the plurality of word line grooves comprises a first word line groove, a second word line groove, and a third word line groove; and the etching the first structure to form, in the first structure, the plurality of word line grooves extending along the direction perpendicular to the first direction comprises: etching each of the plurality of active area structures to form the first word line groove; etching the second isolation layer to form the second word line groove; and etching the bit line structure to form the third word line groove; wherein a bottom surface of the first word line groove is lower than a bottom surface of the second word line groove and a bottom surface of the third word line groove.
4 . The method according to claim 3 , wherein the bottom surface of the third word line groove is flush with or higher than an upper surface of the bit line metal line layer; and an upper surface of the word line conductive connection layer is higher than the bottom surface of the second word line groove and the bottom surface of the third word line groove.
5 . The method according to claim 1 , wherein the etching the first structure to form, in the first structure, the plurality of word line grooves extending along the direction perpendicular to the first direction comprises: etching the first structure to form, in the first structure, a plurality of second grooves extending along the direction perpendicular to the first direction, where a bottom surface of each of the plurality of second grooves is flush with a lower surface of the bit line conductive connection layer; and etching a portion of a given one of the plurality of second grooves corresponding to a given one of the plurality of active area structures to a first position to form the plurality of word line grooves in the first structure, wherein a bottom surface of a given one of the plurality of word line grooves corresponding to the given active area structure is lower than a bottom surface of a given one of the plurality of word line grooves corresponding to the second isolation layer and a bottom surface of a given one of the plurality of word line grooves corresponding to the bit line structure.
6 . The method according to claim 1 , wherein the etching the substrate to form, in the substrate, the plurality of bit line grooves extending along the first direction comprises: forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of first mask strips extending along the first direction, and the plurality of first mask strips are parallel to each other; and etching the substrate covered by the first mask layer to form, in the substrate, a plurality of bit line grooves extending along the first direction.
7 . The method according to claim 1 , wherein the etching the substrate in which the bit line structure is formed to obtain the plurality of active area structures arranged at intervals and the first groove comprises: forming a second mask layer on the substrate where the bit line structure is formed; and etching the substrate covered by the second mask layer to obtain the plurality of active area structures arranged at intervals and the first groove; wherein the second mask layer comprises a plurality of second mask strips arranged at intervals, and a region of each of the plurality of second mask strips intersects with a region of the bit line structure.
8 . The method according to claim 7 , wherein before the etching the substrate covered by the second mask layer to obtain the plurality of active area structures arranged at intervals and the first groove, the method further comprises: providing a third mask layer comprising a plurality of third mask strips extending along a second direction, the plurality of third mask strips being parallel to each other; and cutting each of the plurality of third mask strips into the plurality of second mask strips with a preset length.
9 . The method according to claim 8 , wherein an angle between the first direction and the second direction is between 15° and 30°.
10 . The method according to claim 1 , wherein the sequentially forming the third isolation layer, the word line conductive connection layer and the second insulating layer in each of the plurality of word line grooves comprises: depositing a third isolation layer on a bottom and a side wall of each of the plurality of word line grooves; depositing a first sub word line conductive connection layer on the bottom and the side wall of each of the plurality of word line grooves where the third isolation layer is formed; depositing a second sub word line conductive connection layer in each of the plurality of word line grooves where the first sub word line conductive connection layer is formed; etching back the first sub word line conductive connection layer and the second sub word line conductive connection layer to a second position above the bit line metal line layer, to form the word line conductive connection layer; and depositing a second insulating layer in each of the plurality of word line grooves where the word line conductive connection layer is formed.
11 . The method according to claim 10 , wherein the second position is lower than a midpoint of the bit line conductive connection layer and higher than a lower surface of the bit line conductive connection layer.
12 . The semiconductor structure according to claim 1 , wherein the plurality of word line structures are formed in a plurality of word line grooves, wherein each of the plurality of word line grooves comprises a first word line groove in the plurality of active area structures, a second word line groove in the second isolation layer, and a third word line groove in the bit line structure; and each of the first portion is formed in a corresponding first word line groove, each of the second portion is formed in a corresponding second word line groove, and each of the third portion is formed in a corresponding third word line groove.
13 . The semiconductor structure according to claim 12 , wherein a depth of the word line groove in the active area structures is deeper than that of the word line groove in the second isolation layer.
14 . The method according to claim 1 , wherein a depth of the word line groove in the active area structures is deeper than that of the word line groove in the second isolation layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of PCT/CN2021/125802, filed on Oct. 22, 2021, which claims priority to Chinese Patent Application No. 202110995019.4 titled “METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE” and filed to the State Intellectual Property Office on Aug. 27, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of semiconductor technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. BACKGROUND As a semiconductor memory that randomly writes and reads data at a high speed, a dynamic random access memory (DRAM) is widely used in data storage devices or apparatuses. The DRAM comprises a plurality of duplicate memory cells, each of which includes a capacitor structure and a transistor, where a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor structure. A voltage signal of the word line can control the transistor to be turned on or off, and further, data information stored in the capacitor structure can be read through the bit line, or the data information can be written into the capacitor structure through the bit line for storage. In the related technologies, in the process of fabricating a semiconductor structure, a word line is first fabricated to obtain a word line structure, then a plurality of layers are deposited on the word line structure, and a bit line is formed by etching the plurality of layers for many times. However, multiple etching of the plurality of layers may cause the formed bit line to be narrower at a top and wider at a bottom, which may reduce performance of the semiconductor structure. SUMMARY According to some embodiments, a first aspect of the present disclosure provides a method of fabricating a semiconductor structure to improve performance of the semiconductor structure. Technical solutions of the present disclosure include: providing a substrate; etching the substrate to form, in the substrate, a plurality of bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer in each of the plurality of bit line grooves to obtain a bit line structure; etching the substrate in which the bit line structure is formed to obtain a plurality of active area structures arranged at intervals and a first groove, where the bit line structure intersects with the plurality of active area structures, respectively; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form, in the first structure, a plurality of word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in each of the plurality of word line grooves. According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure, which includes: a substrate comprising a plurality of active area structures arranged at intervals; a plurality of bit line structures formed in the substrate and extending along a first direction, where each of the plurality of bit line structures includes a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer sequentially distributed from bottom to top, and each of the plurality of bit line structures intersects with the plurality of active area structures, respectively; a second isolation layer arranged between the plurality of bit line structures; and a plurality of word line structures formed in the substrate and extending along a direction perpendicular to the first direction, where each of the plurality of word line structures includes a third isolation layer, a word line conductive connection layer and a second insulating layer sequentially distributed from bottom to top. BRIEF DESCRIPTION OF THE DRAWINGS To describe the technical solutions of the embodiments of the present disclosure or the existing technologies more clearly, the accompanying drawings required for describing the embodiments or the existing technologies will be briefly introduced below. Apparently, the accompanying drawings in the following description are merely some embodiments of the present disclosure. To those of ordinary skills in the art, other accompanying drawings may also be derived from these accompanying drawings. FIG. 1 is a schematic diagram of a structure obtained by etching a layer to be processed in the related technologies; FIG. 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; FIG.