US-12622260-B2 - Bottom contact jumpers for stacked field effect transistor semiconductors

Abstract

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (FET) including a top FET and a bottom FET. Additionally, the semiconductor structure includes a bottom source/drain (S/D) contact jumper connection within a gate cut region. The gate cut includes a liner spacer and a dielectric fill within the first liner spacer. Additionally, the bottom S/D contact jumper is within the dielectric fill. The semiconductor structure further includes a top S/D contact fly-over over a bottom S/D contact in contact with the bottom S/D contact jumper. Additionally, the semiconductor structure includes a top S/D access metal track over the bottom S/D contact, through the top S/D contact. Further, the semiconductor structure includes a recessed gate cut liner facing the top S/D contact fly-over. Additionally, the semiconductor structure includes a non-recessed gate cut liner facing a non-fly-over top S/D contact.

Inventors

• James P Mazza
• Koichi Motoyama
• Nicholas Anthony Lanzillo
• Ruilong Xie

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20230919

Claims (20)

1. 1 . A semiconductor structure comprising: a stacked field effect transistor (FET) comprising a top FET and a bottom FET; a bottom source/drain (S/D) contact jumper connection disposed within a gate cut region, wherein the gate cut region comprises a first liner spacer and a dielectric fill disposed within the first liner spacer, and wherein the bottom S/D contact jumper is formed within the dielectric fill; a top S/D contact fly-over disposed over a bottom S/D contact in contact with the bottom S/D contact jumper; a top S/D access metal track disposed over the bottom S/D contact through the top S/D contact; a first gate cut liner facing the top S/D contact fly-over, wherein the first gate cut liner is recessed; and a second gate cut liner facing a non-fly-over top S/D contact, wherein the second gate cut liner is not recessed.
2. 2 . The semiconductor structure of claim 1 , further comprising a single height cell comprising the stacked FET, wherein the top S/D contact fly-over connects a first source of a top FET of the stacked FET, using the bottom S/D contact jumper, to: a drain of the stacked FET; and a second source of a second device.
3. 3 . The semiconductor structure of claim 1 , further comprising a double height cell comprising the stacked FET, wherein the top S/D contact fly-over connects a first source of a bottom FET of the stacked FET, using the bottom S/D contact jumper, to a second drain of a top FET of a second stacked FET.
4. 4 . The semiconductor structure of claim 1 , wherein the top S/D contact fly-over connects the bottom contact jumper of a first cell of the semiconductor structure to a bottom contact jumper of a second cell disposed in a same device layer of the first cell.
5. 5 . The semiconductor structure of claim 1 , wherein the top S/D contact fly-over connects the bottom contact jumper of a first cell of the semiconductor structure to a bottom contact jumper of a second cell disposed in a different device layer from the first cell.
6. 6 . The semiconductor structure of claim 1 , wherein the contact fly-over is disposed over, and in contact with, a top S/D epitaxial of the stacked FET.
7. 7 . The semiconductor structure of claim 1 , wherein the bottom S/D contact is disposed in contact with the second gate cut liner.
8. 8 . A semiconductor structure comprising: a stacked field effect transistor (FET) comprising a top FET and a bottom FET; a bottom source/drain (S/D) contact jumper connection disposed within a gate cut region, wherein the gate cut region comprises a first liner spacer and a dielectric fill disposed within the first liner spacer, and wherein the bottom S/D contact jumper is formed within the dielectric fill; a top S/D contact fly-over disposed over a bottom S/D contact in contact with the bottom S/D contact jumper; a top S/D access metal track disposed over the bottom S/D contact through the top S/D contact; a first gate cut liner facing the top S/D contact fly-over, wherein the first gate cut liner is recessed; and a second gate cut liner facing a non-fly-over top S/D contact, wherein the second gate cut liner is partially recessed.
9. 9 . The semiconductor structure of claim 8 , further comprising a single height cell comprising the stacked FET, wherein the top S/D contact fly-over connects a first source of a top FET of the stacked FET, using the bottom S/D contact jumper, to: a drain of the stacked FET; and a second source of a second device.
10. 10 . The semiconductor structure of claim 8 , further comprising a double height cell comprising the stacked FET, wherein the top S/D contact fly-over connects a first source of a bottom FET of the stacked FET, using the bottom S/D contact jumper, to a second drain of a top FET of a second stacked FET.
11. 11 . The semiconductor structure of claim 8 , wherein the contact fly-over connects the bottom contact jumper of a first cell of the semiconductor structure to a bottom contact jumper of a second cell disposed in a same device layer of the first cell.
12. 12 . The semiconductor structure of claim 8 , wherein the contact fly-over connects the bottom contact jumper of a first cell of the semiconductor structure to a bottom contact jumper of a second cell disposed in a different device layer from the first cell.
13. 13 . The semiconductor structure of claim 8 , wherein the contact fly-over is disposed over, and in contact with, a top S/D epitaxial of the stacked FET.
14. 14 . The semiconductor structure of claim 8 , wherein the bottom S/D contact is disposed in contact with the second gate cut liner.
15. 15 . A method for fabricating a semiconductor structure, the method comprising: forming a top field effect transistor (FET) comprising a top gate, over a bottom FET comprising a bottom gate, wherein the top FET is in contact with a top source/drain (S/D) epitaxial, and wherein the bottom FET is in contact with a bottom S/D epitaxial; forming a cut region at a boundary to a cell comprising the top FET and bottom FET; forming a first liner spacer in the cut region; perform a dielectric fill in the first liner spacer; forming a bottom S/D contact jumper in the dielectric fill; forming a bottom S/D contact with a contact recess; and forming a top S/D contact fly-over over the bottom S/D contact, wherein the bottom S/D contact is in contact with the bottom S/D contact jumper.
16. 16 . The method of claim 15 , further comprising forming a plurality of additional vias.
17. 17 . The method of claim 16 , further comprising forming a plurality of metal lines in contact with one of the plurality of additional vias, wherein the one via connects the plurality of metal lines to the top S/D contact.
18. 18 . The method of claim 17 , wherein the top S/D contact fly-over connects a first source of the top FET, using the bottom S/D contact jumper, to: a drain of the top FET; and a second source of a second device.
19. 19 . The method of claim 18 , wherein the top S/D contact fly-over connects a first source of a bottom FET associated with the top FET, using the bottom S/D contact jumper, to a second drain of a top FET of a stacked FET.
20. 20 . The method of claim 16 , wherein the top S/D contact fly-over connects the bottom contact jumper of a first cell of the semiconductor structure to a bottom contact jumper of a second cell disposed in a same device layer of the first cell.

Description

BACKGROUND The present invention generally relates to semiconductor structures, and more particularly to bottom contact jumpers in stacked field effect transistor (FET) semiconductor structures. Integrated circuit (IC) chips are formed on semiconductor wafers at increasingly smaller scale. In current technology nodes, such as 7, 10 and 14 nanometer technologies, transistor devices are constructed as three-dimensional (3D) fin FET (FINFET) structures. However, chipmakers face a myriad of challenges at 5 nm, 3 nm and beyond. Currently, traditional chip scaling continues to slow as process complexities and costs escalate at each node. A potential solution to this chip scaling problem is gate all around technology. One example of a complex gate all around technology is a stacked FET where nFET and pFET nanowires/nanosheets are vertically stacked on top of each other. In a stacked FET semiconductor, the bottom contacts are in contact with the bottom source/drain (S/D) epitaxial, which is in contact with the bottom FET of the stacked FET. However, in the stacked FET semiconductor, the bottom contacts can create middle of line (MOL) congestion. The MOL congestion can decrease the effectiveness of pin access, and constrain intra-cell routing. SUMMARY Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (FET) including a top FET and a bottom FET. Additionally, the semiconductor structure includes a bottom source/drain (S/D) contact jumper connection within a gate cut region. The gate cut includes a liner spacer and a dielectric fill within the first liner spacer. Additionally, the bottom S/D contact jumper is within the dielectric fill. The semiconductor structure further includes a top S/D contact fly-over over a bottom S/D contact in contact with the bottom S/D contact jumper. Additionally, the semiconductor structure includes a top S/D access metal track over the bottom S/D contact, through the top S/D contact. Further, the semiconductor structure includes a recessed gate cut liner facing the top S/D contact fly-over. Additionally, the semiconductor structure includes a non-recessed gate cut liner facing a non-fly-over top S/D contact. Embodiments are disclosed for a method of fabricating a semiconductor structure. The method includes forming a top FET having a top gate, over a bottom FET comprising a bottom gate. The top FET is in contact with an S/D epitaxial. Further, the bottom FET is in contact with a bottom S/D epitaxial. The method also includes forming a cut region at a boundary to a cell comprising the top FET and bottom FET. Additionally, the method includes forming a first liner spacer in the cut region. Further, the method includes performing a dielectric fill in the first liner spacer. Additionally, the method includes forming a bottom S/D contact jumper in the dielectric fill. Further, the method includes forming a bottom S/D contact with a contact recess. Additionally, the method includes forming a top S/D contact fly-over over the bottom S/D contact, wherein the bottom S/D contact is in contact with the bottom S/D contact jumper. The present Summary is not intended to illustrate each aspect of, every implementation of, and/or every embodiment of the present disclosure. These and other features and advantages will become apparent from the following detailed description of the present embodiment(s), taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are illustrative of certain embodiments and do not limit the disclosure. FIG. 1-1A is a top view and a cross-sectional view of semiconductor structures during intermediate steps of a method for forming bottom contact jumpers of stacked field effect transistor (FET) semiconductors, in accordance with some embodiments of the present disclosure. FIG. 1-1B is cross-sectional views of semiconductor structures during intermediate steps of a method for forming bottom contact jumpers of stacked field effect transistor (FET) semiconductors, in accordance with some embodiments of the present disclosure. FIG. 1-2A is a top view and a cross-sectional view of semiconductor structures during intermediate steps of a method for forming bottom contact jumpers of stacked FET semiconductors, in accordance with some embodiments of the present disclosure. FIG. 1-2B is cross-sectional views of semiconductor structures during intermediate steps of a method for forming bottom contact jumpers of stacked FET semiconductors, in accordance with some embodiments of the present disclosure. FIG. 1-3A is a top view and cross-sectional view of semiconductor structures during intermediate steps of a method for forming botto