US-12622261-B2 - Flexible trackplan for power delivery

Abstract

A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Inventors

• Reinaldo Vega
• Ruilong Xie
• Nicholas Anthony Lanzillo
• Albert M. Chu
• Lawrence A. Clevenger
• Brent A. Anderson
• Takashi Ando
• David Wolpert

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20230812

Claims (18)

1. 1 . A semiconductor device architecture, comprising: a substrate; a device region including active components carried by the substrate; and a plurality of tracks on the substrate, the plurality of tracks comprising conductive lines connecting power and one or more signals to the active components in the device region, wherein a first track includes: a plurality of segments of a conductive line; a first segment in the first track configured to deliver power to the device region; and a second segment in the first track configured to deliver a signal of the one or more signals to the device region; wherein the first segment and the second segment are arranged in the first track, wherein the first segment is positioned on a frontside of the device region, and connected to a third segment on a backside of the device region.
2. 2 . The semiconductor device architecture of claim 1 , wherein: the third segment delivers power to the device region from the backside of the device region; and the third segment is positioned on a second track that includes a fourth segment that connects the signal to the device region.
3. 3 . The semiconductor device architecture of claim 1 , wherein: the first segment is positioned on a frontside of the device region, and connected to a third segment on the frontside of the device region; the third segment delivers power to the device region; and the third segment is positioned on a second track that includes a fourth segment that connects the signal of the one or more signals to the device region.
4. 4 . The semiconductor device architecture of claim 1 , wherein: the first segment includes a first width; and the second segment includes a second width that is equal to the first width.
5. 5 . The semiconductor device architecture of claim 1 , wherein the first segment and the second segment are disconnected.
6. 6 . The semiconductor device architecture of claim 1 , wherein the first segment and the second segment are positioned axially on the first track.
7. 7 . The semiconductor device architecture of claim 1 , wherein the first segment includes a first width and the second segment includes a second width, wherein the first width is not equal to the second width.
8. 8 . A semiconductor device architecture, comprising: a substrate; a device region including active components carried by the substrate; and one or more mixed-use tracks on the substrate, the one or more mixed-use tracks comprising respective conductive lines connecting power and one or more signals to the active components in the device region, wherein a first mixed-use track includes: a first segment selectively dedicated to delivering one of either power or a signal of the one or more signals to the device region; and a second segment in the first mixed-use track, selectively dedicated to deliver the other of either the power or the signal of the one or more signals to the device region, wherein the first segment includes a first width and the second segment includes a second width that is equal to the first width.
9. 9 . The semiconductor device architecture of claim 8 , wherein the first segment is positioned on a frontside of the device region, and connected to a third segment on a backside of the device region.
10. 10 . The semiconductor device architecture of claim 9 , wherein: the third segment delivers power to the device region from the backside of the device region; and the third segment is positioned on a second mixed-use track that includes a fourth segment that connects the signal of the one or more signals to the device region.
11. 11 . The semiconductor device architecture of claim 8 , wherein: the first segment is positioned on a frontside of the device region, and connected to a third segment on the frontside of the device region; the third segment delivers power to the device region; and the third segment is positioned on a second mixed-use track that includes a fourth segment that connects the signal of the one or more signals to the device region.
12. 12 . The semiconductor device architecture of claim 8 , wherein the first segment and the second segment are disconnected.
13. 13 . The semiconductor device architecture of claim 8 , wherein the first segment and the second segment are positioned axially on the same first mixed-use track.
14. 14 . The semiconductor device architecture of claim 8 , wherein: the first segment includes a first width; the second segment includes a second width; and the first width is not equal to the second width.
15. 15 . A semiconductor device, comprising: a substrate; a first interconnect system on the substrate; a first device region in the first interconnect system; a first track of conductive lines in the first interconnect system; a first segment in the first track configured to deliver power to the first device region; a second segment in the first track that connects a first signal to the first device region; a second interconnect system on the substrate; a second device region in the second interconnect system; a second track of conductive lines in the second interconnect system; a third segment in the second track configured to deliver power to the second device region; a fourth segment in the second track that connects a second signal to the second device region; and a wire connect connecting the second segment in the first track of the first interconnect system to the fourth segment in the second track of conductive lines in the second interconnect system, or to a terminal not present in the first interconnect system.
16. 16 . The semiconductor device of claim 15 , further comprising: a fifth segment in a third track of the first interconnect system, wherein the fifth segment is configured to deliver power to the first device region; and a fill cell in the first interconnect system, wherein the fifth segment is connected to the first segment in the first track.
17. 17 . The semiconductor device of claim 15 , wherein: the first segment and the second segment are disconnected from each other in the first track of conductive lines; and the third segment and the fourth segment are disconnected from each other in the second track of conductive lines.
18. 18 . The semiconductor device of claim 15 , wherein: the first segment and the second segment are positioned axially on the first track of conductive lines; and the third segment and the fourth segment are positioned axially on the second track of conductive lines.

Description

BACKGROUND Technical Field The present disclosure generally relates to semiconductor device architecture, and more particularly, to a flexible trackplan for power delivery. Description of the Related Art In semiconductor device manufacture, conventional methods use frontside contact schemes during wafer processing. In frontside contact schemes, the overlay margins involved in forming frontside contacts are fairly accurate and easy to align with features on the frontside of the device. Some technologies use more backside formed connections. Forming contacts from the backside presents various benefits as well as new challenges including for example, where to position conductive lines to maximize the footprint of area available while still providing power or signal to different parts of the device region. Generally speaking, whether laying out an architecture for either frontside delivery or backside delivery, the conductive lines are dedicated for either power delivery or signal delivery. Sometimes the length of a track for a circuit may be wholly occupied by for example, a power rail. The same line cannot be used for both power and signal delivery, otherwise a short circuit occurs. If different lines sharing a track are lined up end to end, the lines generally also share the same functional designation for either power delivery or signal delivery. Delivering power from one rail through a device to signal lines typically involves that one track be wholly devoted to carrying power to multiple adjacent signal lines. Circuit layouts are limited however in the options available to position power rails adjacent to signal lines. Much of the circuit layout area is inefficiently used where signal lines are not adjacent power rails. For example, an entire track may be occupied by a power rail, but only a short section of the power rail may be used to deliver power to the device. SUMMARY According to an embodiment of the present disclosure, a semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track. According to another embodiment of the present disclosure, a semiconductor device includes a substrate and a device region including active components carried by the substrate. One or more mixed-use tracks on the substrate include conductive lines connecting power and signals to the active components in the device region. A first mixed-use track includes a first segment selectively dedicated to delivering one of either power or a signal to the device region. A second segment in the same first mixed-use track, is selectively dedicated to deliver the other of either power or the signal to the device region. According to another embodiment of the present disclosure, a semiconductor device includes a substrate and a first interconnect system on the substrate. A first device region is in the first interconnect system. A first track of conductive lines is in the first interconnect system. A first segment is in the first track configured to deliver power to the first device region. A second segment in the first track connects a first signal to the first device region. A second interconnect system is on the substrate. A second device region is in the second interconnect system. A second track of conductive lines is in the second interconnect system. A third segment in the second track is configured to deliver power to the second device region. A fourth segment in the second track connects a second signal to the second device region. A wire connect connects the second segment in the first track of the first interconnect system to the fourth segment in the second track of the second interconnect system, or to a terminal not present in the first interconnect system. The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures. BRIEF DESCRIPTION OF THE DRAWINGS The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps. FIG. 1 is a schematic end view of a power delivery architecture in a conventional semiconductor dev