US-12622262-B2 - Low-stress passivation layer

US12622262B2US 12622262 B2US12622262 B2US 12622262B2US-12622262-B2

Abstract

Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Inventors

Hsiang-Ku Shen
Wen-Ling CHANG
Chen-Chiu Huang
Chia-Nan LIN
Man-Yun WU
Wen-Tzu Chen
Sean Yang
Dian-Hao CHEN
Chi-Hao Chang
Ching-Wei Lin

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20230112

Claims (20)

1 . A method of fabricating a semiconductor device, comprising: receiving a workpiece that includes a redistribution layer disposed over and electrically coupled to an interconnect structure; patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, wherein corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess, and wherein the patterning the redistribution layer includes an etching process that provides a rounding of the corners of the first conductive feature and the second conductive feature; depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess; depositing a nitride layer over the first dielectric layer; and removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
2 . The method of claim 1 , wherein the etching process includes a first etching step and a second etching step, wherein the first etching step is performed using a first Cl 2 /BCl 3 gas ratio, and wherein the second etching step is performed using a second Cl 2 /BCl 3 gas ratio different than the first Cl 2 /BCl 3 gas ratio.
3 . The method of claim 2 , wherein the first Cl 2 /BCl 3 gas ratio is less than about 2, and wherein the second Cl 2 /BCl 3 gas ratio is in a range between about 2 and about 3.
4 . The method of claim 1 , further comprising: after the patterning the redistribution layer and prior to depositing the first dielectric layer, performing an argon ion bombardment step primarily directed at the corners of the first conductive feature and the second conductive feature to provide an additional rounding of the corners of the first conductive feature and the second conductive feature.
5 . The method of claim 4 , wherein the argon ion bombardment is performed for a duration of time that is determined based on a pattern density of the redistribution layer.
6 . The method of claim 1 , wherein the removing the portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature is performed as part of depositing a second dielectric layer over the nitride layer.
7 . The method of claim 6 , wherein the depositing the second dielectric layer includes depositing the second dielectric layer using a high-density plasma chemical vapor deposition (HDPCVD) process.
8 . The method of claim 7 , wherein the HDPCVD process includes alternating deposition and etching-back cycles performed at different bias values and at different pressure.
9 . The method of claim 6 , wherein the first dielectric layer and the second dielectric layer are deposited using different deposition techniques.
10 . The method of claim 1 , wherein the depositing the first dielectric layer forms overhang regions at the corners of the first conductive feature and the second conductive feature due to an accumulation of the first dielectric layer.
11 . A method, comprising: providing a substrate including a redistribution layer disposed over a multi-layer interconnect (MLI) structure; depositing a nitride layer over the redistribution layer; and forming a recess extending through the nitride layer and the redistribution layer, wherein the recess separates a first portion of the redistribution layer from a second portion of the redistribution layer, and wherein the forming the recess includes an etching process that provides a rounding of a corner of at least one of the first portion of the redistribution layer and the second portion of the redistribution layer on either side of the recess; wherein after forming the recess, the nitride layer remains disposed over top surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer, while sidewall surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer are free of the nitride layer.
12 . The method of claim 11 , further comprising: prior to depositing the nitride layer, depositing a first dielectric layer over the redistribution layer; depositing the nitride layer over the first dielectric layer; and forming the recess extending through the nitride layer, the first dielectric layer, and the redistribution layer.
13 . The method of claim 11 , wherein the forming the recess includes the etching process that further provides the rounding of corners of both the first portion of the redistribution layer and the second portion of the redistribution layer on either side of the recess.
14 . The method of claim 11 , wherein the etching process includes a first etching step and a second etching step, wherein the first etching step is performed using a first Cl 2 /BCl 3 gas ratio, and wherein the second etching step is performed using a second Cl 2 /BCl 3 gas ratio different than the first Cl 2 /BCl 3 gas ratio.
15 . The method of claim 14 , wherein the first Cl 2 /BCl 3 gas ratio is less than the second Cl 2 /BCl 3 gas ratio.
16 . The method of claim 13 , further comprising: after forming the recess, performing an argon ion bombardment step primarily directed at the corners of the first portion of the redistribution layer and the second portion of the redistribution layer to provide an additional rounding of the corners of the first portion of the redistribution layer and the second portion of the redistribution layer.
17 . The method of claim 16 , wherein the argon ion bombardment is performed for a duration of time that is determined based on a pattern density of the redistribution layer.
18 . A semiconductor device, comprising: a redistribution layer including a first conductive feature and a second conductive feature separated by a recess, wherein corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess; a first passivation layer disposed over the redistribution layer and within the recess; and a contact feature extending through the first passivation layer and electrically coupled to the first conductive feature; wherein the first passivation layer includes a nitride layer having a discontinuity region that is substantially aligned with the corners of the first conductive feature and the second conductive feature, wherein the first passivation layer further includes a first dielectric layer interposing the redistribution layer and the nitride layer along upper sidewall portions of the recess and along top surfaces of the first and second conductive features, and wherein the first dielectric layer further interposes a second passivation layer underlying the redistribution layer and the nitride layer along lower sidewall portions of the recess and along a bottom surface of the recess; and wherein a top surface of the first conductive feature defines a first plane, wherein a sidewall of the first conductive feature adjacent to the recess defines a second plane that intersects the first plane, and wherein a rounding of the corner of the first conductive feature is defined at least partly by a distance between the intersection of the first and second planes and a surface of the corner of the first conductive feature.
19 . The semiconductor device of claim 18 , wherein the first passivation layer further includes a second dielectric layer disposed over the nitride layer.
20 . The semiconductor device of claim 19 , wherein the first dielectric layer and the second dielectric layer are formed of different materials.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Application No. 63/380,688, filed Oct. 24, 2022, the entirety of which is incorporated by reference herein. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. For example, ICs are formed on a semiconductor substrate that may be cut into individual device dies or IC chips. Each IC chip may be further attached (such as by bonding) to an interposer, a reconstituted wafer, a circuit board, or another die to form a package or a device. To meet various routing needs, a redistribution layer (RDL) of conductive metal lines may be formed on an IC chip to reroute bond connections from the edge to the center of the chip, or generally to disperse bond connections to an area greater than that of the IC chip. One or more passivation layers are implemented around the RDL to protect the semiconductor surface from electrical shorts, stress, and chemical contaminants. However, some passivation layers are prone to stress and cracks during subsequent annealing processes and may lead to voids or cracks between adjacent metal contacts. Therefore, although existing passivation layers and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments. FIG. 1 is a flow chart of a method for fabricating a semiconductor device in accordance with embodiments of the present disclosure; FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are cross-sectional views of a workpiece at various stages of fabrication according to the method of FIG. 1, in accordance with some embodiments; FIGS. 3A and 3B provide cross-sectional views of a portion of the workpiece during patterning of a redistribution layer, according to some embodiments; FIGS. 3C and 3D provide enlarged views of a portion of the workpiece illustrated in FIG. 3 after the redistribution layer is patterned, in accordance with some embodiments; FIG. 14 is a flow chart of a method for fabricating a semiconductor device in accordance with some alternative embodiments of the present disclosure; and FIGS. 15, 16, 17, 18, 19, 20, 21, and 22 are cross-sectional views of a workpiece at various stages of fabrication according to the method of FIG. 14, in accordance with some embodiments. DETAILED DESCRIPTION It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The s