US-12622263-B2 - Forming dielectric film with high resistance to tilting

US12622263B2US 12622263 B2US12622263 B2US 12622263B2US-12622263-B2

Abstract

A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Inventors

Ming-Tsung Lee
Yi-Wen PAN
Tzu-Nung Lu
You-Lan LI
Chung-Chi Ko

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220222

Claims (20)

1 . A method comprising: depositing a dielectric layer over a substrate, wherein the depositing the dielectric layer comprises adjusting a flow rate of a nitrogen-containing precursor, so that the dielectric layer comprises: a bottom portion comprising nitrogen and having a constant nitrogen atomic percentage; a middle portion having a higher nitrogen atomic percentage than the bottom portion of the dielectric layer; and an upper portion having a lower nitrogen atomic percentage than the middle portion of the dielectric layer; etching the dielectric layer to form an opening, wherein a first conductive feature underlying the dielectric layer is exposed to the opening; depositing a sacrificial spacer layer extending into the opening; patterning the sacrificial spacer layer, wherein a bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a first vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a first ring; forming a second conductive feature in the opening, wherein the second conductive feature is encircled by the first ring, and is over and electrically coupled to the first conductive feature, and wherein the second conductive feature comprises a substantially straight edge extending from a bottom surface level of the bottom portion to a top surface level of the upper portion; and removing at least a portion of the first ring to form an air spacer.
2 . The method of claim 1 , wherein the depositing the dielectric layer comprises depositing a high-k dielectric material.
3 . The method of claim 1 further comprising forming a metal capping layer over the second conductive feature, wherein an interface between the metal capping layer and the second conductive feature is coplanar with a top surface of the dielectric layer, wherein the metal capping layer comprises an extension portion extending into the air spacer.
4 . The method of claim 1 further forming a metal capping layer over the second conductive feature, wherein the first ring is removed after the metal capping layer is formed.
5 . The method of claim 1 , wherein the depositing the dielectric layer is performed using a first precursor comprising silicon, carbon, and hydrogen, and a second precursor comprising nitrogen.
6 . The method of claim 1 , wherein the depositing the dielectric layer is performed without using porogen.
7 . The method of claim 1 further comprising forming an additional dielectric layer over the sacrificial spacer layer and sealing the air spacer, wherein at a time after the air spacer is formed, a residue portion of the first ring is left underlying the additional dielectric layer.
8 . A method comprising: forming a first conductive feature over a substrate; depositing a first etch stop layer over the first conductive feature; depositing a dielectric layer over the first etch stop layer, wherein the dielectric layer comprises nitrogen therein, wherein the depositing the dielectric layer comprises: depositing a bottom portion having a first nitrogen atomic percentage; depositing a middle portion over the bottom portion, wherein the middle portion has a second nitrogen atomic percentage higher than the first nitrogen atomic percentage; and depositing an upper portion over the middle portion, wherein the upper portion has a third nitrogen atomic percentage lower than the second nitrogen atomic percentage; forming a second conductive feature in the dielectric layer and the first etch stop layer, wherein the second conductive feature is over and contacting the first conductive feature, wherein the second conductive feature is encircled by an air spacer, wherein sidewalls of the second conductive feature are exposed to the air spacer, and wherein the air spacer extends from substantially a bottom surface of the bottom portion to a top surface of the upper portion; and depositing a second etch stop layer over and contacting the dielectric layer, wherein the second etch stop layer is further over the second conductive feature.
9 . The method of claim 8 , wherein the depositing the dielectric layer comprises depositing a high-k dielectric material.
10 . The method of claim 8 , wherein the forming the air spacer comprises: forming a sacrificial spacer layer, wherein the second conductive feature is formed in a region encircled by the sacrificial spacer layer; and etching to remove first part of the sacrificial spacer layer and to form the air spacer, wherein a top surface of a second part of the sacrificial spacer layer is underlying, and is exposed to, the air spacer.
11 . The method of claim 8 further comprising performing a selective deposition process to form a metal cap over the second conductive feature, wherein a portion of the metal cap is at a location lower than a top surface of the second conductive feature.
12 . A method comprising: forming a first conductive feature; forming a dielectric layer over the first conductive feature, wherein the forming the dielectric layer comprises adjusting a flow rate of a nitrogen-containing precursor, so that a middle portion of the dielectric layer has a higher nitrogen atomic percentage than a respective lower portion of the dielectric layer, and an upper portion of the of the dielectric layer has a lower nitrogen atomic percentage than the middle portion; forming a second conductive feature over and electrically coupling to the first conductive feature, wherein the second conductive feature comprises: a diffusion barrier; and a metallic material in a basin formed by the diffusion barrier, wherein the second conductive feature comprises a substantially straight edge extending from a bottom surface level of the lower portion to a top surface level of the upper portion; and forming an air spacer encircling a top portion of the second conductive feature, wherein the air spacer is encircled by the dielectric layer, and wherein the dielectric layer comprises a high-k dielectric material that comprises nitrogen.
13 . The method of claim 12 , wherein no dielectric material is between the second conductive feature and the air spacer.
14 . The method of claim 12 , wherein the forming the air spacer comprises removing a sacrificial spacer layer between the dielectric layer and the second conductive feature, and wherein after the removing the sacrificial spacer layer, a residue portion of the sacrificial spacer layer is left.
15 . The method of claim 10 , wherein before the air spacer is formed, the first part of the sacrificial spacer layer overlaps the second part of the sacrificial spacer layer, with first edges of the first part of the sacrificial spacer layer being vertically aligned to respective second edges of the second part of the sacrificial spacer layer.
16 . The method of claim 12 , wherein the forming the dielectric layer comprises implanting nitrogen, so that the upper portion has the lower nitrogen atomic percentage than the respective lower portion.
17 . The method of claim 8 , wherein the depositing the dielectric layer comprises adjusting a flow rate of a nitrogen-containing precursor continuously.
18 . The method of claim 1 , wherein the the middle portion and the upper portion of the dielectric layer are formed using a same method by adjusting flow rates of same precursors.
19 . The method of claim 1 , wherein the air spacer extends from the bottom surface level of the bottom portion to the top surface level of the upper portion.
20 . The method of claim 8 , wherein the second conductive feature comprises a substantially straight edge extending from the bottom surface of the bottom portion to the top surface of the upper portion.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of the following provisionally filed U.S. Patent application: Application No. 63/264,196, filed on Nov. 17, 2021, and entitled “High Mechanical Strength IMD Layer for Air Gap Process on BEOL,” which application is hereby incorporated herein by reference. BACKGROUND Integrated circuit devices such as transistors are formed on semiconductor wafers. The devices are interconnected through metal lines and vias to form functional circuits, wherein the metal lines and vias are formed in back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, the metal lines and vias are formed in low-k dielectric layers, which typically have k values lower than 3.8, lower than 3.0, or lower than 2.5. In the formation of the metal lines and vias in a low-k dielectric layer, the low-k dielectric layer is etched to form trenches and via openings. The etching of the low-k dielectric layer may involve forming a patterned hard mask over the low-k dielectric material, and form trenches using the patterned hard mask as an etching mask. Via openings are also formed underlying the trenches. The trenches and the via openings are then filled with a metallic material, which may comprise copper. A Chemical Mechanical Polish (CMP) process is then performed to remove excess portions of the metallic material over the low-k dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-8, 9A, 9B, 10-14, and 15A illustrate the cross-sectional views of intermediate stages in the formation of an interconnect structure including air spacers in accordance with some embodiments. FIG. 15B illustrates the cross-sectional view of a dual damascene structure without being surrounded by any air spacer in accordance with some embodiments. FIG. 15C illustrates a top view of an air spacer in accordance with some embodiments. FIG. 16 illustrates some example precursors for forming a dielectric layer in accordance with some embodiments. FIGS. 17 and 18 illustrate some example profiles of nitrogen atomic percentage values in accordance with some embodiments. FIGS. 19-22 illustrate the cross-sectional views of intermediate stages in the formation of an interconnect structure in accordance with some embodiments. FIG. 23 illustrates a precursor including a Si—C—Si bond in accordance with some embodiments. FIG. 24 illustrates some precursors free from Si—C—Si bonds in accordance with some embodiments. FIG. 25 illustrates the schematic view of layers in a wafer in accordance with some embodiments. FIGS. 26 and 27 illustrate the carbon concentrations in some dielectric layers in accordance with some embodiments. FIG. 28 illustrates a process flow for forming conductive features and air spacers in accordance with some embodiments. FIG. 29 illustrates a process flow for forming conductive features in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. An interconnect structure and the method of forming the same are provided. In accordance with some emb