US-12622265-B2 - Stacked semiconductor device including a cooling structure

Abstract

A stacked semiconductor device includes a cooling structure to increase the cooling efficiency of the stacked semiconductor device. The cooling structure includes various types of cooling components integrated into the stacked semiconductor device that are configured to remove and/or dissipate heat from dies of the stacked semiconductor device. In this way, the cooling structure reduces device failures and permits the stacked semiconductor device to operate at greater voltages, greater speeds, and/or other increased performance parameters by removing and/or dissipating heat from the stacked semiconductor device.

Inventors

• Jen-Yuan Chang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20230808

Claims (20)

1. 1 . A stacked semiconductor device, comprising: a first die; a second die bonded with the first die at a bonding layer; a first dielectric layer around side surfaces of the first die; a second dielectric layer around side surfaces of the second die; and a cooling structure including: a plurality of heat removal structures configured to remove heat from at least one of the first die or the second die; and a plurality of vertical heat dissipation structures configured to dissipate the heat, wherein a first vertical heat dissipation structure of the plurality of vertical heat dissipation structures is formed in the first dielectric layer, wherein second multiple vertical heat dissipation structures, of the plurality of vertical heat dissipation structures, are formed in the second dielectric layer, wherein at least one horizontal heat removal structure, of the plurality of heat removal structures, is formed in the bonding layer and above a portion of the first die, and wherein the at least one horizontal heat removal structure is physically connected to the first vertical heat dissipation structure and the second multiple vertical heat dissipation structures.
2. 2 . The stacked semiconductor device of claim 1 , wherein at least one of a heat removal structure of the plurality of heat removal structures or a vertical heat dissipation structure of the plurality of vertical heat dissipation structures is surrounded by: a guard ring, and an intermetal dielectric buffer ring.
3. 3 . The stacked semiconductor device of claim 1 , wherein at least one of a heat removal structure of the plurality of heat removal structures or a vertical heat dissipation structure of the plurality of vertical heat dissipation structures includes: a round structure, or a polygon structure.
4. 4 . The stacked semiconductor device of claim 1 , wherein the plurality of heat removal structures extend in a first plane of the stacked semiconductor device; and wherein the plurality of vertical heat dissipation structures extend in a second plane, of the stacked semiconductor device, that is approximately perpendicular to the first plane.
5. 5 . The stacked semiconductor device of claim 1 , wherein one or more of the plurality of vertical heat dissipation structures include a hollow structure that is configured to dissipate the heat through convection.
6. 6 . The stacked semiconductor device of claim 1 , further comprising: an inter-die cooling structure that extends through the first die and the second die, wherein the inter-die cooling structure is connected to one or more of the plurality of heat removal structures.
7. 7 . The stacked semiconductor device of claim 1 , wherein the first die and the second die are connected by a through substrate via (TSV).
8. 8 . The stacked semiconductor device of claim 1 , wherein at least one of a heat removal structure of the plurality of heat removal structures or a vertical heat dissipation structure of the plurality of vertical heat dissipation structures includes a plurality of fins.
9. 9 . A stacked semiconductor device, comprising: a first die; a second die bonded with the first die at a bonding layer; a first dielectric layer around side surfaces of the first die; a second dielectric layer around side surfaces of the second die; and a thermoelectric cooling structure, that extends into at least a portion of the first die and into at least a portion of the second die, comprising: a cold side, included in the first die, configured to cool the first die, a hot side, included in the second die, configured to receive heat from the cold side, an n-type semiconductor structure that thermally connects the cold side included in the first die and the hot side included in the second die, a p-type semiconductor structure that thermally connects the cold side, included in the first die, and the hot side included in the second die, a first vertical heat dissipation structure formed in the first dielectric layer, a second plurality of vertical heat dissipation structures formed in the second dielectric layer, and a horizontal heat removal structure formed in the bonding layer and below a portion of the first die, wherein the horizontal heat removal structure is physically connected to the first vertical heat dissipation structure and the second plurality of vertical heat dissipation structures.
10. 10 . The stacked semiconductor device of claim 9 , wherein the n-type semiconductor structure extends through a substrate of the second die; and wherein the p-type semiconductor structure extends through the substrate of the second die.
11. 11 . The stacked semiconductor device of claim 9 , wherein the n-type semiconductor structure and the p-type semiconductor structure are thermally connected to the cold side included in the first die and the hot side included in the second die in parallel; and wherein the n-type semiconductor structure and the p-type semiconductor structure are configured to be electrically connected to an electrical source in series.
12. 12 . The stacked semiconductor device of claim 9 , wherein the n-type semiconductor structure is a first n-type semiconductor structure that extends through a substrate of the first die; wherein the p-type semiconductor structure is a first p-type semiconductor structure that extends through the substrate of the first die; and wherein the stacked semiconductor device further comprises: a second n-type semiconductor structure that extends through a substrate of the second die; and a second p-type semiconductor structure that extends through the substrate of the second die, wherein the second n-type semiconductor structure and the second p-type semiconductor structure thermally connect the cold side included in the first die and the hot side included in the second die.
13. 13 . The stacked semiconductor device of claim 9 , wherein the hot side included in the second die comprises: a plurality of heat removal structures configured to remove heat from at least one of the first die or the second die; and a plurality of heat dissipation structures configured to dissipate heat.
14. 14 . The stacked semiconductor device of claim 13 , wherein the plurality of heat dissipation structures comprise one or more vertical heat dissipation structures.
15. 15 . A stacked semiconductor device, comprising: a first die; a second die bonded with the first die at a bonding layer; a first dielectric layer around side surfaces of the first die; a second dielectric layer around side surfaces of the second die; and a cooling structure including: an inter-die cooling structure formed in and through the first die and the second die, wherein the inter-die cooling structure is configured to remove heat from the first die and the second die; a plurality of heat removal structures configured to remove heat from at least one of the first die or the second die; and a plurality of heat dissipation structures configured to remove heat from at least one of the first die or the second die, wherein a first heat dissipation structure of the plurality of heat dissipation structures is formed in the first dielectric layer, wherein second multiple heat dissipation structures, of the plurality of heat dissipation structures, are formed in the second dielectric layer, wherein at least one horizontal heat removal structure, of the plurality of heat removal structures, is formed in the bonding layer and above a portion of the first die, and wherein the at least one horizontal heat removal structure is physically connected to the first heat dissipation structure and the second multiple heat dissipation structures.
16. 16 . The stacked semiconductor device of claim 15 , wherein the inter-die cooling structure is connected to one or more heat removal structures of the plurality of heat removal structures.
17. 17 . The stacked semiconductor device of claim 15 , further comprising another inter-die cooling structure.
18. 18 . The stacked semiconductor device of claim 15 , wherein the plurality of heat removal structures are arranged horizontally in the stacked semiconductor device.
19. 19 . The stacked semiconductor device of claim 15 , wherein the plurality of heat dissipation structures are arranged perpendicular to the plurality of heat removal structures.
20. 20 . The stacked semiconductor device of claim 15 , wherein third multiple heat dissipation structures, of the plurality of heat dissipation structures, are formed above the second die.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This Patent Application is a divisional of U.S. patent application Ser. No. 17/304,983, filed Jun. 29, 2021, and entitled “STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE,” which claims priority to U.S. Patent Application No. 63/201,300, filed on Apr. 22, 2021, and entitled “STACKED SEMICONDUCTOR DEVICE INCLUDING A HEAT DISSIPATION STRUCTURE.” The disclosures of the prior Applications are considered part of and are incorporated by reference into this Patent Application. BACKGROUND Bonding in the semiconductor industry is a technique that may be used to form stacked semiconductor devices and three-dimensional integrated circuits. Some examples of bonding include wafer to wafer bonding, die to wafer bonding, and die to die bonding, fusion bonding, and hybrid bonding, among other examples. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a diagram of an example environment in which systems and/or methods described herein may be implemented. FIG. 2 is a diagram of an example stacked semiconductor device described herein. FIG. 3 is a diagram of an example portion described herein of the stacked semiconductor device of FIG. 2. FIGS. 4A-4T are diagrams of an example implementation described herein. FIGS. 5A-5C are diagrams of example cooling component configurations of a cooling structure described herein. FIGS. 6A-6D are diagrams of example portions described herein of the stacked semiconductor device of FIG. 2. FIG. 7 is a diagram of example components of one or more devices of FIG. 1 described herein. FIG. 8 is a flowchart of an example process relating to forming a stacked semiconductor device described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A stacked semiconductor device is a semiconductor device that includes a plurality of semiconductor dies. Examples of stacked semiconductor devices include a system on integrated circuit (SoIC) device, a micro electromechanical system (MEMS) device, and a chip on wafer on substrate (CoWoS) device. A stacked semiconductor device accumulates heat during operation, which may decrease the performance of the stacked semiconductor device and/or may cause device failures. Some implementations described herein provide a stacked semiconductor device that includes a cooling structure to increase the cooling efficiency of the stacked semiconductor device. The cooling structure includes various types of cooling components integrated into the stacked semiconductor device that are configured to remove and/or dissipate heat from the dies of the stacked semiconductor device. In this way, the cooling structure reduces device failures and permits the stacked semiconductor device to operate at greater voltages, greater speeds, and/or other increased performance parameters by removing and/or dissipating heat from the stacked semiconductor device. FIG. 1 is a diagram of an example environment 100 in which systems and/or methods described herein may be implemented. As shown in FIG. 1, environment 100 may include a plurality of semicondu