US-12622271-B2 - Cooling cover and packaged semiconductor device including the same

US12622271B2US 12622271 B2US12622271 B2US 12622271B2US-12622271-B2

Abstract

Cooling covers including trapezoidal cooling chambers for cooling packaged semiconductor devices and methods of forming the same are disclosed. In an embodiment, a cooling cover for a semiconductor device includes an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.

Inventors

Chung-Jung Wu
Sheng-Tsung HSIAO
JEN YU WANG
Tung-Liang Shao
Chih-Hang Tung

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220627

Claims (20)

1 . A cooling cover comprising: a base having a major surface extending in a first plane, the major surface being configured to thermally connect to a semiconductor device; an inlet, the inlet having a first fluid-flow cross-sectional area and having a first flow-path height extending in a first direction perpendicular to the first plane; an inlet distributor in fluid communication with the inlet, the inlet distributor having a second fluid-flow cross-sectional area greater than the first fluid-flow cross-sectional area and having a second flow-path height greater than the first flow-path height in the first direction; an outlet; an outlet collector in fluid communication with the outlet; and a cooling chamber having a first side in fluid communication with the inlet distributor, the cooling chamber having a trapezoidal shape in a cross-sectional view, wherein the cooling chamber has a third flow-path height less than the second flow-path height in the first direction at an interface between the cooling chamber and the inlet distributor and has a fourth flow-path height less than the third flow-path height in the first direction at a second interface between the cooling chamber and the outlet collector, and further wherein the cooling chamber has a third fluid-flow cross-sectional area less than the second fluid-flow cross-sectional area at the second interface, and further wherein the outlet collector has a fifth flow-path height greater than the fourth flow-path height in the first direction and greater than a sixth flow-path height of the outlet in the first direction; and wherein the outlet has a fourth fluid-flow cross-sectional area less than the third fluid-flow cross-sectional area.
2 . The cooling cover of claim 1 , wherein the cooling chamber has a first height adjacent the inlet, wherein the cooling chamber has a second height adjacent the outlet, and wherein the first height is greater than the second height.
3 . The cooling cover of claim 2 , wherein a ratio of the first height to the second height is from 1 to 50.
4 . The cooling cover of claim 2 , wherein the first height is less than 2000 μm, and wherein the second height is less than 1000 μm.
5 . The cooling cover of claim 1 , further comprising an adhesive encircling the cooling chamber.
6 . The cooling cover of claim 1 , wherein the cooling cover includes a groove encircling the cooling chamber, and further comprising a gasket within the groove.
7 . The cooling cover of claim 1 , wherein the cooling chamber is configured to directly cool a backside of an integrated circuit device using a liquid coolant.
8 . An apparatus comprising: a packaged semiconductor device, the packaged semiconductor device comprising a first integrated circuit chip, the first integrated circuit chip comprising a plurality of channels on a backside of the first integrated circuit chip; and a cooling cover on the packaged semiconductor device, wherein the cooling cover comprises: a fluid inlet having a first fluid-flow cross-sectional area and a first flow-path height extending in a first direction perpendicular to a major surface of the packaged semiconductor device; an inlet distributor having a second fluid flow cross-section area and having a second flow-path height in the first direction, greater than the first flow-path height; a cooling chamber on the first integrated circuit chip, a first side of the cooling chamber having a third flow-path height less than the second flow-path height and being in fluid communication with the inlet distributor; an outlet collector having a fourth flow-path height greater than the third flow-path height, wherein a second side of the cooling chamber, opposite the first side of the cooling chamber, has a third fluid-flow cross-sectional area less than the second fluid flow cross-sectional area and is in fluid communication with the outlet collector; an outlet in fluid communication with the outlet collector, the outlet having a fourth fluid-flow cross-sectional area less than the third fluid-flow cross-sectional area, and having a fifth flow-path height less than the fourth flow-path height; and a gasket surrounding the cooling chamber and contacting the packaged semiconductor device.
9 . The apparatus of claim 8 , wherein the cooling cover is attached to the packaged semiconductor device by a screw-type fastener, wherein the screw-type fastener extends through a portion of the packaged semiconductor device and a portion of the cooling cover.
10 . The apparatus of claim 8 , wherein the cooling cover is attached to the packaged semiconductor device by a clamp-type fastener, the clamp-type fastener contacting a first surface of the cooling cover opposite the packaged semiconductor device and a second surface of the packaged semiconductor device opposite the cooling cover.
11 . The apparatus of claim 8 , wherein the cooling cover further comprises an inlet and an outlet, wherein the cooling chamber is in fluid communication with the inlet and the outlet, and wherein the cooling chamber has a trapezoidal shape in a cross-sectional view.
12 . The apparatus of claim 11 , wherein the cooling chamber has a first height adjacent the inlet, wherein the cooling chamber has a second height adjacent the outlet, wherein the first height is less than 2000 μm, and wherein the second height is less than 1000 μm.
13 . The apparatus of claim 8 , wherein the cooling chamber is configured to flow a liquid coolant across the plurality of channels in a direction perpendicular to longitudinal axes of the plurality of channels.
14 . The apparatus of claim 8 , wherein the cooling chamber is configured to flow a liquid coolant across the plurality of channels with an increasing mass flux.
15 . A method of cooling a packaged semiconductor device comprising: providing a packaged semiconductor device; attaching a mating surfaced of a cooling cover to the packaged semiconductor device by passing a screw assembly through a bolt hole in the cooling cover and a corresponding bolt hole in the packaged semiconductor device; and flowing a liquid coolant through the cooling cover by flowing the liquid coolant through an inlet having a first flow-path height, measured in a first direction perpendicular to the mating surface, and having a first fluid-flow cross-sectional area, flowing the liquid coolant from the inlet to an inlet distributor having a second flow-path height, greater than the first flow-path height in the first direction, and having a second fluid-flow cross-sectional area less, flowing the liquid coolant from the inlet distributor to a cooling chamber having a cooling chamber flow-path height that decreases in the direction of the liquid coolant flow from a third flow-path height to a fourth flow-path height less than the third flow-path height, the cooling chamber further having a fluid-flow cross-sectional area that decreases in the direction of the liquid coolant flow to a third fluid-flow cross-sectional area less than the second fluid-flow cross-sectional area, flowing the liquid coolant from the cooling chamber to an outlet collector having a fifth flow-path height greater than the third flow-path height, and flowing the liquid coolant from the outlet collector to an outlet having a fourth fluid-flow cross-sectional area, less than the third fluid-flow cross-sectional area, and further having a sixth flow-path height less than the fifth flow-path height.
16 . The method of claim 15 , wherein the surface of the packaged semiconductor device is provided with a plurality of channels formed therein.
17 . The method of claim 15 , wherein the liquid coolant comprises water.
18 . The method of claim 15 , wherein the cooling cover is attached to the packaged semiconductor device by an adhesive, and wherein the adhesive is placed in a channel encircling a cooling chamber of the cooling cover.
19 . The method of claim 15 , wherein the cooling cover is attached to the packaged semiconductor device by screw-type fasteners, and wherein the screw-type fasteners apply pressure to a gasket encircling a cooling chamber of the cooling cover to prevent the liquid coolant from escaping the cooling chamber.
20 . The method of claim 15 , wherein the cooling cover comprises a cooling chamber on the packaged semiconductor device, wherein the cooling chamber has a sloped surface opposite the packaged semiconductor device, wherein the sloped surface of the cooling chamber increases the flowrate of the liquid coolant as the liquid coolant moves across the sloped surface of the cooling chamber.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, and the like). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, smaller packaging techniques of semiconductor dies have emerged. As semiconductor technologies further advance, stacked and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated at least partially on separate substrates and then physically and electrically bonded together in order to form a functional device. Such bonding processes utilize sophisticated techniques, and improvements are desired. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A and 1B illustrate a perspective view and a cross-sectional view, respectively, of a cooling cover, in accordance with some embodiments. FIGS. 2 through 13 illustrate cross-sectional and top-down views of intermediate stages in the manufacturing of a package structure, in accordance with some embodiments. FIGS. 14A through 14D illustrate cross-sectional views of package structures including cooling covers, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various embodiments provide a cooling cover, methods for manufacturing the cooling cover, a packaged semiconductor device including the cooling cover, and methods for manufacturing the packaged semiconductor device. The packaged semiconductor device may include one or more chips with channels being formed in backsides thereof. The cooling cover may provide liquid coolant directly to the channels. As such, the cooling cover provides direct cooling to the chips, which improves heat transfer between the chips and the liquid coolant. The cooling cover includes a cooling chamber through which the liquid coolant flows across the backsides of the chips. A surface of the cooling chamber opposite the chips is tilted such that a height of the cooling chamber at an inlet over the chips is greater than a height of the cooling chamber at an outlet over the chips. This causes the flowrate (e.g., the mass flux) of the liquid cooling to increase as the liquid coolant flows across the backsides of the chips. This improves the evenness of cooling provided across the backsides of the chips. As such, the cooling cover may provide improves heat transfer from the chips to the liquid coolant, even cooling of the chips, improved device performance, and reduced device defects caused by overheating of the chips. Embodiments will be described with respect to a specific context, namely a die-interposer-substrate stacked package using chip-on-wafer-on-substrate (CoWoS) processing. Ho