US-12622275-B2 - Semiconductor package having cooling systems with flow control devices within substrates

Abstract

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

Inventors

• Seungwon Im
• Oseob Jeon
• Byoungok Lee
• Yoonsoo LEE
• JoonSeo Son
• Dukyong LEE
• Changyoung PARK

Assignees

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date

20260505

Application Date

20240326

Claims (13)

1. 1 . A semiconductor package comprising: a first cover coupled to a first substrate, the first substrate coupled to a first die; a first cooling system comprised within the first substrate; a second cover coupled to a second substrate, the second substrate coupled to a second die; a second cooling system comprised within the second substrate; and a spacer coupled between a surface on the first die facing the second substrate and a surface of the second die facing the first substrate; wherein the first cooling system and the second cooling system each comprise a flow control device configured to induce turbulent flow of a cooling medium passing through the first cooling system and the second cooling system.
2. 2 . The semiconductor package of claim 1 , wherein the flow control device comprises a heat slug with fins.
3. 3 . The semiconductor package of claim 1 , wherein the spacer is directly coupled to the first die and the second die.
4. 4 . The semiconductor package of claim 1 , wherein the each of the first substrate and the second substrate comprise an outer layer directly coupled to a dielectric layer.
5. 5 . The semiconductor package of claim 4 , wherein the first substrate comprises a patterned layer directly coupled between the dielectric layer and the first die.
6. 6 . The semiconductor package of claim 1 , wherein the first cover and the second cover comprise a water jacket.
7. 7 . The semiconductor package of claim 1 , wherein the first cover and the second cover each comprises nickel plated copper.
8. 8 . A semiconductor package comprising: a first cover coupled to a first substrate, the first substrate comprising an outer layer, the first substrate coupled to a first die; a first cooling system comprised within the outer layer; a second cover coupled to a second substrate, the second substrate comprising a second outer layer, the second substrate coupled to a second die; a second cooling system comprised within the second outer layer; and a spacer coupled between the first die and the second die; wherein the first substrate comprises a dielectric layer directly coupled to the outer layer and the second substrate comprises a second dielectric layer directly coupled to the second outer layer; and wherein the first cooling system and the second cooling system each comprise a flow control device configured to induce turbulent flow of a cooling medium passing through the first cooling system and the second cooling system.
9. 9 . The semiconductor package of claim 8 , wherein the flow control device comprises a heat slug with fins.
10. 10 . The semiconductor package of claim 8 , wherein the spacer is directly coupled between a surface of the first die facing the second substrate and a surface of the second die facing the first substrate.
11. 11 . The semiconductor package of claim 8 , wherein the first substrate comprises a patterned layer directly coupled between the dielectric layer and the first die.
12. 12 . The semiconductor package of claim 8 , wherein the first cover and the second cover comprise a water jacket.
13. 13 . The semiconductor package of claim 8 , wherein the first cover and the second cover each comprises nickel plated copper.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This document claims the benefit of the filing date of U.S. Provisional Patent Application 62/491,948, entitled “Integrated Circuit Direct Cooling Systems and Related Methods” to Seungwon Im et al. which was filed on Apr. 28, 2017, the disclosure of which is hereby incorporated entirely herein by reference. This application is a divisional application of the earlier U.S. Utility Patent Application to Seungwon Im et al. entitled “Integrated Circuit Direct Cooling Systems and Related Methods,” application Ser. No. 17/457,100, filed Dec. 1, 2021, which application is a divisional application of the earlier U.S. Utility Patent Application to Seungwon Im et al. entitled “Semiconductor Package having a Spacer with a Junction Cooling Pipe,” now issued as U.S. Pat. No. 11,201,105, which application a divisional application of the earlier U.S. Utility Patent Application to Seungwon Im et al. entitled “Integrated Circuit Direct Cooling Systems and Related Methods,” now issued as U.S. Pat. No. 10,607,919, the disclosures of each of which are hereby incorporated entirely herein by reference. BACKGROUND 1. Technical Field Aspects of this document relate generally to semiconductor packages with cooling systems. More specific implementations involve semiconductor packages with direct junction cooling systems. 2. Background Integrated circuits generate excess heat. Due to this, some semiconductor packages generally include or are coupled to a cooling system that dissipates the excess heat to improve reliability and prevent the integrated circuit from failing due to overheating. Conventionally, semiconductor packages have been cooled by systems such as a single external heat sink, dual heat sinks, external cooling modules, and external cooling water jackets coupled to the outside of the substrate or package. SUMMARY Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer including a junction cooling pipe therethrough. Implementations of semiconductor packages may include one, all, or any of the following: The wall of the junction cooling pipe may include a dielectric material. The spacer may include a plurality of junction cooling pipes therethrough, a cross section of the plurality of junction cooling pipes fully comprised within a cross section of the spacer. The package may include a second spacer between the second die and a third die, the third die coupled to the second substrate. The package may include a third substrate coupled to a third die, a fourth substrate coupled to a fourth die, and a second spacer coupled between and coupled to the third die and the fourth die, the second spacer comprising a junction cooling pipe therethrough, wherein the face of the second substrate may be coupled to a face of the third substrate. The junction cooling pipe may include a finned heat exchanger, one of integrally formed therewith and coupled thereto. Implementations of semiconductor packages may include a first substrate coupled to a first die, a first plurality of junction cooling pipes, each junction cooling pipe of the first plurality of junction cooling pipes at least partially embedded in the first substrate, a second substrate coupled to a second die, a second plurality of junction cooling pipes, each junction cooling pipe of the second plurality of junction cooling pipes at least partially embedded in the second substrate, and a spacer coupled between the first die and the second die. Implementations of semiconductor packages may include one, all, or any of the following: The first substrate and the second substrate may include one of a dielectric layer, a patterned layer, and both a dielectric layer and a patterned layer. The first plurality of junction cooling pipes may be fully embedded in the first substrate. The second plurality of junction cooling pipes may be fully embedded in the second substrate. The package may include a first cover coupled to the first substrate, wherein the first plurality of junction cooling pipes may be partially embedded in the first cover. The package may include a second cover coupled to the second substrate, wherein the second plurality of junction cooling pipes may be partially embedded in the second cover. The first plurality of junction cooling pipes and the second plurality of junction cooling pipes may each include one of heat pipes, water pipes, and a combination of heat pipes and water pipes. Each pipe of the first plurality of junction cooling pipes and each pipe of the second plurality of junction cooling pipes may be coated with a dielectric material. Implementations of semiconductor packages may include a first cover coupled to a first substrate, the first substrate coupled