US-12622276-B2 - Interposer including a copper edge seal ring structure and methods of forming the same

US12622276B2US 12622276 B2US12622276 B2US 12622276B2US-12622276-B2

Abstract

An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures. The edge seal ring structure may include a vertical stack of metallic ring structures that are free of aluminum and laterally surround the package-side bump structures and the redistribution interconnect structures.

Inventors

Hong-Seng Shue
Yao-Chun Chuang
Yu-Tse Su
Chen-Shien Chen
Ching-Wen Hsiao
Ming-Da Cheng

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date: 20260505
Application Date: 20240613

Claims (20)

1 . A method of forming a structure, comprising: forming interconnect-level dielectric material layers embedding redistribution interconnect structures and interconnect-level metallic ring structures over a carrier substrate, wherein the interconnect-level metallic ring structures laterally surround the redistribution interconnect structures; forming at least one dielectric capping layer over the interconnect-level dielectric material layers; forming metallic pad structures and a pad-level metallic ring structure through, and over, the at least one dielectric capping layer; forming a bonding-level dielectric layer over the metallic pad structures; forming via openings through the bonding-level dielectric layer over the metallic pad structures; and forming die-side bump structures over the bonding-level dielectric layer on a respective one of the metallic pad structures, wherein an edge seal ring structure is provided, which comprises an assembly of the pad-level metallic ring structure and the interconnect-level metallic ring structures, and laterally surrounds the redistribution interconnect structures and the metallic pad structures, and vertically extends through each of the interconnect-level dielectric material layers and the at least one dielectric capping layer.
2 . The method of claim 1 , wherein the interconnect-level dielectric material layers comprise organic polymer materials.
3 . The method of claim 2 , further comprising forming package-side bump structures embedded in a package-side dielectric material layer over the carrier substrate, wherein the interconnect-level dielectric material layers are formed over the package-side dielectric material layer, and a subset of the redistribution interconnect structures is formed on the package-side bump structures.
4 . The method of claim 3 , wherein the package-side dielectric material layer comprises a package-side silicon nitride layer, and is in direct contact with a bottommost organic polymer material among the organic polymer materials.
5 . The method of claim 4 , wherein bonding surfaces of the package-side bump structures are formed within a first horizontal plane within which an entirety of a horizontal surface of the package-side dielectric material layer is formed.
6 . The method of claim 5 , wherein the edge seal ring structure vertically extends from the first horizontal plane to a second horizontal plane including distal planar surfaces of the metallic pad structures through the package-side dielectric material layer, the interconnect-level dielectric material layers, and the at least one dielectric capping layer.
7 . The method of claim 6 , wherein the edge seal ring structure comprises a vertical stack of metallic ring structures that are free of aluminum and laterally surrounds the package-side bump structures and each of the redistribution interconnect structures.
8 . The method of claim 7 , wherein: the vertical stack of metallic ring structures comprises a package-side metallic ring structure that is embedded within the package-side dielectric material layer; inner sidewalls of the package-side metallic ring structure contact an inner portion of the package-side dielectric material layer that is laterally surrounded by the package-side metallic ring structure; and outer sidewalls of the package-side metallic ring structure contact an outer portion of the package-side dielectric material layer that laterally surrounds the package-side metallic ring structure.
9 . The method of claim 7 , further comprising: attaching a packaging substrate to the package-side bump structures employing an array of solder material portions; and applying an underfill material portion around the array of solder material portions directly on a horizontal surface of the package-side dielectric material layer and directly on a bottom surface of the vertical stack of metallic ring structures, wherein the vertical stack of metallic ring structures is not in direct contact with any solder material.
10 . The method of claim 1 , further comprising attaching at least one semiconductor die to the die-side bump structures employing a first array of solder material portions.
11 . The method of claim 1 , wherein the bonding-level dielectric layer covers an entire area of the pad-level metallic ring structure and contacts a top surface, an inner sidewall, and an outer sidewall of the pad-level metallic ring structure.
12 . The method of claim 1 , further comprising forming a moat trench and pad-level via cavities through the at least one dielectric capping layer, wherein a top surface of the interconnect-level metallic ring structures is exposed at a bottom of the moat trench and top surfaces of the redistribution interconnect structures are exposed underneath the pad-level via cavities.
13 . The method of claim 12 , further comprising depositing and patterning a copper layer in the moat trench and the pad-level via cavities and over the at least one dielectric capping layer, wherein pattern portions of the copper layer comprise the metallic pad structures and the pad-level metallic ring structure.
14 . A method of forming a device structure, comprising: forming package-side bump structures embedded in a package-side dielectric material layer over a carrier wafer, wherein the package-side dielectric material layer comprises a package-side silicon nitride layer, wherein bonding surfaces of the package-side bump structures are formed within a first horizontal plane within which an entirety of a horizontal surface of the package-side dielectric material layer is formed; forming interconnect-level dielectric material layers embedding redistribution interconnect structures over the package-side dielectric material layer; forming at least one dielectric capping layer on the interconnect-level dielectric material layers; forming a bonding-level dielectric layer located on the at least one dielectric capping layer; forming metallic pad structures, wherein the metallic pad structures portions include pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, wherein distal planar surfaces of the metallic pad structures that are most distal from the first horizontal plane are located within a second horizontal plane; forming die-side bump structures located on the distal planar surfaces of the metallic pad structures; forming an edge seal ring structure vertically extending from the first horizontal plane to the second horizontal plane; and attaching at least one semiconductor die to the die side bump structures while the carrier wafer is attached to the package-side dielectric material layer; bonding a packaging substrate to the package-side bump structures using an array of solder material portions; and applying an underfill material portion around the array of solder material portions directly on a horizontal surface of the package-side dielectric material layer and directly on a bottom surface of the edge seal ring structure, wherein the edge seal ring structure is not in direct contact with any solder material.
15 . The method of claim 14 , further comprising detaching the carrier wafer from the package-side dielectric material layer, whereby an assembly vertically extending from the package-side dielectric material layer to the die-side bump structures comprises an interposer.
16 . The method of claim 14 , wherein: the interconnect-level dielectric material layers comprise organic polymer materials; and a bottommost organic polymer material among the organic polymer materials is formed directly on the package-side silicon nitride layer.
17 . The method of claim 14 , wherein the edge seal ring structure laterally surrounds the redistribution interconnect structures and the metallic pad structures and vertically extends through each of the interconnect-level dielectric material layers and the at least one dielectric capping layer.
18 . A method of forming a device structure, comprising: forming package-side bump structures embedded in a package-side dielectric material layer over a carrier substrate, wherein bonding surfaces of the package-side bump structures are formed within a first horizontal plane within which an entirety of a horizontal surface of the package-side dielectric material layer is formed; forming interconnect-level dielectric material layers comprising organic polymer materials and embedding redistribution interconnect structures over the package-side dielectric material layer; forming at least one dielectric capping layer consisting essentially of at least one inorganic dielectric material on the interconnect-level dielectric material layers; forming a bonding-level dielectric layer comprising a stack of a dielectric passivation layer and a bonding-level polymer layer on the at least one dielectric capping layer; forming metallic pad structures, wherein the metallic pad structures include pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, wherein distal planar surfaces of the metallic pad structures that are most distal from the first horizontal plane are located within a second horizontal plane; forming an edge seal ring structure comprising a vertical stack of metallic ring structures and laterally surrounding the package-side bump structures and each of the redistribution interconnect structures, wherein no metallic structure is embedded outside of the vertical stack of metallic ring structures within the interposer; and forming die-side bump structures on the distal planar surfaces of the metallic pad structures.
19 . The method of claim 18 , wherein: the vertical stack of metallic ring structures comprises a package-side metallic ring structure that is embedded within the package-side dielectric material layer; inner sidewalls of the package-side metallic ring structure contact an inner portion of the package-side dielectric material layer that is laterally surrounded by the package-side metallic ring structure; and outer sidewalls of the package-side metallic ring structure contact an outer portion of the package-side dielectric material layer that laterally surrounds the package-side metallic ring structure.
20 . The method of claim 18 , further comprising: bonding at least one semiconductor die to the die-side bump structures employing an array of first solder material portions; detaching the carrier substrate from the package-side dielectric material layer; and bonding a packaging substrate to the package-side bump structures employing an array of second solder material portions.

Description

RELATED APPLICATIONS This application is a divisional application of U.S. application Ser. No. 17/412,530 entitled “Interposer Including a Copper Edge Seal Ring Structure and Methods of Forming the Same,” filed on Aug. 26, 2021, the entire contents of which are incorporated herein by reference for all purposes. BACKGROUND A fan-out wafer level package (FOWLP) may use an interposer between semiconductor dies and a package substrate. An acceptable interposer possesses sufficient mechanical strength to withstand bonding processes used to attach the semiconductor dies and the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a vertical cross-sectional view of an exemplary structure after formation of redistribution interconnect structures embedded in interconnect-level dielectric material layers and interconnect-level metallic ring structures according to an embodiment of the present disclosure. FIG. 1B is a top-down view of a unit die area of the exemplary structure of FIG. 1A. FIG. 1C is a top-down view of a region C of the exemplary structure of FIG. 1B. FIG. 1D is a vertical cross-sectional view along the vertical plane D-D′ of FIG. 1C. FIG. 2A is a top-down view of a region of the exemplary structure after formation of at least one dielectric capping layer according to an embodiment of the present disclosure. FIG. 2B is a vertical cross-sectional view along the plane B-B′ of FIG. 2A. FIG. 3A is a top-down view of a region of the exemplary structure after formation of pad-level via cavities and a moat trench through the at least one dielectric capping layer according to an embodiment of the present disclosure. FIG. 3B is a vertical cross-sectional view along the plane B-B′ of FIG. 3A. FIG. 4A is a top-down view of a region of the exemplary structure after formation of a metallic seed layer according to an embodiment of the present disclosure. FIG. 4B is a vertical cross-sectional view along the plane B-B′ of FIG. 4A. FIG. 5A is a top-down view of a region of the exemplary structure after formation of a patterned photoresist layer according to an embodiment of the present disclosure. FIG. 5B is a vertical cross-sectional view along the plane B-B′ of FIG. 5A. FIG. 6A is a top-down view of a region of the exemplary structure after electroplating copper according to an embodiment of the present disclosure. FIG. 6B is a vertical cross-sectional view along the plane B-B′ of FIG. 6A. FIG. 7A is a top-down view of a region of the exemplary structure after removal of the patterned photoresist layer according to an embodiment of the present disclosure. FIG. 7B is a vertical cross-sectional view along the plane B-B′ of FIG. 7A. FIG. 8A is a top-down view of a region of the exemplary structure after removal of unmasked portions of the metallic seed layer according to an embodiment of the present disclosure. FIG. 8B is a vertical cross-sectional view along the plane B-B′ of FIG. 8A. FIG. 9A is a top-down view of a region of the exemplary structure after formation of a dielectric passivation layer according to an embodiment of the present disclosure. FIG. 9B is a vertical cross-sectional view along the plane B-B′ of FIG. 9A. FIG. 10A is a top-down view of a region of the exemplary structure after formation of a bonding-level polymer layer and formation of bonding-level via cavities according to an embodiment of the present disclosure. FIG. 10B is a vertical cross-sectional view along the plane B-B′ of FIG. 10A. FIG. 11A is a vertical cross-sectional view of the exemplary structure after formation of die-side bump structures and attaching solder balls to the die-side bump structures according to an embodiment of the present disclosure. FIG. 11B is a top-down view of a unit die area of the exemplary structure of FIG. 11A. FIG. 11C is a top-down view of a region C of the exemplary structure of FIG. 11B. FIG. 11D is a vertical cross-sectional view along the vertical plane D-D′ of FIG. 11C. FIG. 12 is a vertical cross-sectional view of the exemplary structure after attaching semiconductor dies to the organic interposers according to an embodiment of the present disclosure. FIG. 13 is a vertical cross-sectional view of the exemplary structure after formation of fan-out wafer-level packages according to an embodiment of the present disclosure. FIG. 14 is a vertical cross-sectional view of the exemplary structure after dicing the fan-out wafer-level packages according to an embodiment of the present disclosure. FIG. 15 is a vertical cross-sectional view of the exemplary structure after attaching a package substrate to the fan-out wafer-level package accor