US-12622283-B2 - Semiconductor devices and data storage systems including the same

Abstract

A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

Inventors

• Ahreum Lee
• Jimo GU
• Jiyoung Kim
• Sukkang SUNG

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230222

Priority Date

20220517

Claims (19)

1. 1 . A semiconductor device, comprising: a plate layer; and an align key on the plate layer, wherein the align key includes a first align layer and a second align layer connected to the first align layer, the first align layer has a first length in a first direction, a second length in a second direction, and an air gap in the first align layer, wherein the air gap is covered from above by the first align layer, the first direction is perpendicular to an upper surface of the plate layer, the second length is smaller than the first length, the second direction is perpendicular to the first direction, the second align layer is on the first align layer, the second align layer has a third length, and the third length is smaller than the second length in the second direction.
2. 2 . The semiconductor device of claim 1 , wherein the first align layer and the second align layer form a single layer.
3. 3 . The semiconductor device of claim 1 , wherein the align key includes a bent portion according to a difference in width in a region in which the first align layer is connected to the second align layer.
4. 4 . The semiconductor device of claim 1 , wherein an entirety of the second align layer overlaps the first align layer in the first direction.
5. 5 . The semiconductor device of claim 1 , wherein the first align layer has a fourth length in a third direction perpendicular to the second direction, and the second align layer has a fifth length smaller than the fourth length in the third direction.
6. 6 . The semiconductor device of claim 1 , wherein the second align layer has a sixth length smaller than the first length in the first direction.
7. 7 . The semiconductor device of claim 1 , wherein the first align layer and the second align layer each include a reflective material.
8. 8 . The semiconductor device of claim 1 , wherein a width of a lower surface of the first align layer is smaller than a width of an upper surface of the first align layer, and a width of a lower surface of the second align layer is smaller width than a width of an upper surface of the second align layer.
9. 9 . The semiconductor device of claim 1 , wherein the second align layer is shifted from a central axis of the first align layer in the second direction.
10. 10 . The semiconductor device of claim 1 , wherein a ratio of the first length to the second length is in a range of 10:1 to 100:1.
11. 11 . A semiconductor device, comprising: a substrate including a plate layer; an align key on the substrate, the align key including a first align layer and a second align layer stacked in order in a first direction perpendicular to an upper surface of the plate layer, the first align layer and the second align layer being connected to each other; and a light transmissive layer on a side surface of the second align layer, wherein the first align layer and the second align layer overlap each other in the first direction, and wherein, in a plan view, the second align layer is within an outer perimeter of the first align layer.
12. 12 . The semiconductor device of claim 11 , wherein a length of the first align layer is different than a length of the second align layer in a second direction, and the second direction is perpendicular to the first direction.
13. 13 . The semiconductor device of claim 11 , wherein the first align layer includes an air gap therein, and the second align layer does not include an air gap.
14. 14 . The semiconductor device of claim 11 , further comprising: a vertical structure on the substrate, wherein the semiconductor device includes a first region and a second region, memory cells and the vertical structure are in the first region, the align key is in the second region, and a level of the vertical structure corresponds to a level of at least the first align layer.
15. 15 . The semiconductor device of claim 14 , wherein the vertical structure includes a first vertical structure layer and a second vertical structure layer, the first vertical structure layer is on a same level as a level of the first align layer, and the second vertical structure layer is on a level corresponding to a level of the second align layer.
16. 16 . A data storage system, comprising: a semiconductor storage device including a plate layer, circuit devices below the plate layer, and an input/output pad electrically connected to the circuit devices, the semiconductor storage device having a first region and a second region; and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device, wherein the semiconductor storage device further includes: a stack structure in the first region, the stack structure including gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer, a channel structure penetrating through the stack structure and in contact with the plate layer in the first region, a through-via extending in the first direction and penetrating through the stack structure in the first region, the through-via being electrically connected to the circuit devices, and the through-via including a first via layer and a second via layer stacked in order in the first direction, a mold structure including horizontal sacrificial layers stacked and spaced apart from each other in the first direction in the second region, and an align key penetrating through the mold structure in the second region, the align key extending in the first direction, and the align key including a first align layer and a second align layer stacked in order in the first direction, wherein the first align layer and the second align layer overlap each other in the first direction, and wherein an air gap is in the first align layer, and the air gap is covered from above by the first align layer.
17. 17 . The data storage system of claim 16 , wherein the first via layer and the second via layer overlap each other in the first direction.
18. 18 . The data storage system of claim 16 , wherein a level of a lower end of the through-via is different from a level of a lower end of the align key.
19. 19 . The data storage system of claim 16 , wherein; the air gap extends in the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2022-0060351, filed on May 17, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND Example embodiments of the present disclosure relate to a semiconductor device and a data storage system including the same. A semiconductor device able to store high-capacity data in a data storage system requiring data storage may be necessary. Accordingly, a method for increasing data storage capacity of a semiconductor device has been researched. For example, as a method for increasing data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally, instead of memory cells arranged two-dimensionally, has been suggested. SUMMARY An example embodiment of the present disclosure provides a semiconductor device having improved reliability. An example embodiment of the present disclosure provides a data storage system including a semiconductor device having improved reliability. According to an example embodiment of the present disclosure, a semiconductor device may include a plate layer; and an align key on the plate layer. The align key may include a first align layer and a second align layer connected to the first align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The second direction may be perpendicular to the first direction. The second align layer may be on the first align layer. The second align layer may have a third length. The third length may be smaller than the second length in the second direction. According to an example embodiment of the present disclosure, a semiconductor device may include a substrate including a plate layer; an align key on substrate; and a light transmissive layer. The align key may include a first align layer and a second align layer stacked in order in a first direction perpendicular to an upper surface of the plate layer. The first align layer and the second align layer may be connected to each other. The light transmissive layer may be on a side surface of the second align layer. The first align layer and the second align layer may overlap each other in the first direction. According to an example embodiment of the present disclosure, a data storage system may include a semiconductor storage device including a plate layer, circuit devices below the plate layer, and an input/output pad electrically connected to the circuit devices, the semiconductor storage device having a first region and a second region, and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device. The semiconductor storage device may further include a stack structure in the first region, the stack structure including gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer; a channel structure penetrating through the stack structure and in contact with the plate layer in the first region; a through-via extending in the first direction and penetrating through the stack structure in the first region, the through-via being electrically connected to the circuit devices, and the through-via including a first via layer and a second via layer stacked in order in the first direction; a mold structure including horizontal sacrificial layers stacked and spaced apart from each other in the first direction in the second region; and an align key penetrating through the mold structure in the second region, the align key extending in the first direction, and the align key including a first align layer and a second align layer stacked in order in the first direction. The first align layer and the second align layer may overlap each other in the first direction. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in combination with the accompanying drawings, in which: FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; FIGS. 2A and 2B are a plan view and a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; FIGS. 4A and 4B are cross-sectional views illustrating a semiconductor device according to an