US-12622284-B2 - Solder volume for flip-chip bonding

US12622284B2US 12622284 B2US12622284 B2US 12622284B2US-12622284-B2

Abstract

Methods, systems, and structures relating to flip-chip bonding are described. A processor can determine a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate. The plurality of target solder volumes can be variable among the plurality of pads. The processor can determine different thicknesses of different portions of a layer of resist to be deposited across the surface of the substrate. The different thicknesses can define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes.

Inventors

Toyohiro Aoki
Katsuyuki Sakuma
Hiroyuki Mori
Koki Nakamura
Takashi Hisada

Assignees

INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230221

Claims (8)

1 . A method comprising: determining, by a processor, a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate, wherein the plurality of target solder volumes is variable among the plurality of pads; and determining, by the processor, different thicknesses, spanning in a direction perpendicular to the surface of the substrate, of different portions of a layer of resist to be deposited across the surface of the substrate, wherein the different thicknesses define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes.
2 . The method of claim 1 , further comprising: receiving, by the processor, a surface topology of the surface of the substrate, wherein the surface topology indicates depth measurements between peaks of the plurality of pads and the surface of the substrate; and based on the surface topology, generating, by the processor, pad density adjustment data indicating an adjustment to a pad density of the surface of the substrate for achieving the determined different thicknesses of the different portions of the layer of resist.
3 . The method of claim 2 , further comprising: based on the surface topology, determining, by the processor, pad densities of different portions of the surface of the substrate; identifying, by the processor, at least one portion of the surface of the substrate having a pad density that does not satisfy a threshold; and generating, by the processor, the pad density adjustment data for adjusting the pad density of the at least one portion of the surface of the substrate.
4 . The method of claim 3 , further comprising: identifying, by the processor, a portion of the surface of the substrate that has a pad density lower than the threshold; and generating, by the processor, the pad density adjustment data to indicate an addition of at least one imitation pad to the at least one portion of the surface of the substrate, wherein the addition of the at least one imitation pad increases the pad density of the identified portion of the surface, and the increased pad density increases a thickness of the layer of resist at the identified portion of the surface.
5 . The method of claim 3 , wherein identifying the at least one portion of the surface comprises: identifying, by the processor, a portion of the surface of the substrate that has a pad density greater than the threshold; and generating, by the processor, the pad density adjustment data to indicate a removal of at least one pad from the at least one portion of the surface of the substrate, wherein the removal of the at least one pad decreases the pad density of the identified portion of the surface, and the decreased pad density decreases a thickness of the layer of resist at the identified portion of the surface.
6 . The method of claim 1 , further comprising generating, by the processor, exposure adjustment data for adjusting exposure levels of a mask being used for patterning the layer of resist, wherein the adjustment to the exposure levels of the mask is for achieving the determined different thicknesses of the different portions of the layer of resist.
7 . The method of claim 6 , generating the exposure adjustment data comprises: identifying, by the processor, a portion of the surface of the substrate that corresponds to a particular thickness among the different thicknesses; and generating the exposure adjustment data to adjust an exposure level of a portion of the mask that corresponds to the identified portion of the surface of the substrate, wherein the adjusted exposure level causes the layer of resist to have the particular thickness.
8 . The method of claim 6 , wherein the mask is a grayscale mask, and the exposure adjustment data indicates adjustment to intensity levels of the grayscale mask.

Description

BACKGROUND The present application relates to systems and methods for optimizing solder volume for flip-chip bonding based on variable resist thickness. Structures having high-density interconnections between functional chips such as central processing unit (CPU), graphics processing unit (GPU), high bandwidth memory (HBM), or other types of chips, allow for achieving high-performance computing. Various advanced packaging technologies with fine-pitch interposers and fine-pitch bonding can be used for forming these structures. For example, flip chip bonding can be used for connecting chips to an interposer that provides signal routing among the chips, thus interconnecting the chips to form one package. SUMMARY In one embodiment, a method for flip-chip bonding is generally described. The method can include determining, by a processor, a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate. The plurality of target solder volumes is variable among the plurality of pads. The method can further include determining, by the processor, different thicknesses of different portions of a layer of resist to be deposited across the surface of the substrate. The different thicknesses can define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes. In one embodiment, a semiconductor package formed by flip-chip bonding is generally described. The semiconductor package can include a first substrate and a second substrate bonded to the first substrate via a plurality of solder joints. The plurality of solder joints can have variable volume. The variable volume can be based on different thicknesses of different portions of a layer of resist being deposited on a surface of the first substrate. The layer of resist can define a plurality of solder resist openings on a plurality of pads of the first substrate. The surface of the first substrate can include at least one imitation pad that is not bonded by the plurality of solder joints. The different thicknesses can be based on the at least one imitation pad. In one embodiment, a method for flip-chip bonding is generally described. The method can include depositing a layer of resist on a surface of a first substrate. The first substrate can include a plurality of pads, different portions of the layer of resist have different thicknesses, and the different thicknesses can be based on a plurality of predetermined target solder volumes. The method can further include forming a plurality of solder resist openings on the plurality of pads. The sizes of the plurality of solder resist openings can be defined by the different thicknesses of the layer of resist, and the sizes of the plurality of solder resist openings can comply with the plurality of predetermined target solder volumes. The method can further include filling the plurality of solder resist openings with solder. The method can further include removing the layer of resist from the surface of the substrate. A plurality of solder bumps can be formed in response to the removing, where the plurality of solder bumps can have same solder volume as the plurality of predetermined target solder volumes. The method can further include bonding a second substrate to the first substrate via the plurality of solder bumps. Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example package that can be formed by implementing optimized solder volume for flip-chip bonding in one embodiment. FIG. 2A illustrates an example of target solder volumes for implementing optimized solder volume for flip-chip bonding in one embodiment. FIG. 2B illustrates an example of a layer of resist with variable thickness in one embodiment. FIG. 2C illustrates an example of solder resist openings formed by a layer of resist with variable resist thickness in one embodiment. FIG. 2D illustrates another example of solder resist openings formed by a layer of resist with variable resist thickness in one embodiment. FIG. 2E illustrates an example of solder deposited in the solder resist openings shown in FIG. 2C. FIG. 2F illustrates an example of solder bumps formed by an implementation of optimized solder volume for flip-chip bonding in one embodiment. FIG. 2G illustrates an example of a combination of a first substrate and a second substrate as a result of an implementation of optimized solder volume for flip-chip bonding in one embodiment. FIG. 2H illustrates an example package that can be formed by the combination shown in FIG. 2G. FIG. 3A illustrates another example of a layer of resist with variable resist thickness in one embodiment. FIG. 3B illustrates another example of solder resist openings formed by a layer of res