US-12622287-B2 - Multilayer glass substrate

Abstract

Embodiments herein relate to systems, apparatuses, techniques, or processes for packages that include multiple glass layers within the package. In embodiments, a core of the package may include multiple glass layers that may be bonded together, or may be separated by a dielectric layer between glass layers. In embodiments, the glass layers may include one or more electrically conductive features, such as conductive vias, conductive planes, electrical pads, electrical traces, redistribution layer, capacitors, inductors, active dies and/or passive dies. Other embodiments may be described and/or claimed.

Inventors

• Telesphor Kamgaing

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20211221

Claims (20)

1. 1 . A substrate comprising: a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features; a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features; wherein the first side of the first glass layer is coupled with the side of the second glass layer; and a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer, wherein the third glass layer includes one or more electrically conductive features therein; and a die coupled to the electrically conductive features in the third glass layer.
2. 2 . The substrate of claim 1 , wherein the one or more electrically conductive features of the first glass layer or the one or more electrically conductive features of the second glass layer include a plurality of electrically conductive vias, wherein a pitch of the plurality of electrically conductive vias ranges from 50 μm to 100 μm.
3. 3 . The substrate of claim 1 , wherein the first side of the first glass layer is electrically coupled with the side of the second glass layer.
4. 4 . The substrate of claim 1 , wherein the one or more electrically conductive features include a selected one or more of: a conductive via, a conductive plane, an electrical pad, an electrical trace, a redistribution layer, a capacitor, an inductor, an active die, or a passive die.
5. 5 . The substrate of claim 1 , wherein the first side of the first glass layer and the side of the second glass layer are directly coupled.
6. 6 . The substrate of claim 5 , wherein the first side of the first glass layer and the side of the second glass layer are hybrid bonded.
7. 7 . The substrate of claim 1 , wherein the first side of the first glass layer includes a cavity; and further including an electrical component within the cavity of the first glass layer.
8. 8 . The substrate of claim 7 , wherein the electrical component within the cavity of the first glass layer is electrically coupled with the one or more electrically conductive features of the second glass layer.
9. 9 . The substrate of claim 7 , wherein the electrical component within the cavity of the first glass layer is electrically coupled with a routing layer at a bottom of the cavity.
10. 10 . The substrate of claim 7 , wherein the electrical component is a selected one of: an active component or a passive component.
11. 11 . The substrate of claim 1 , wherein the first side of the first glass layer includes a first copper pad with a surface that is substantially parallel to a plane of the first side of the first glass layer, wherein the side of the second glass layer includes a second copper pad with a surface that is substantially parallel to the plane of the first side of the first glass layer, and wherein the first copper pad and the second copper pad at least partially overlap each other with respect to a direction perpendicular to the plane of the first side of the first glass layer; and further comprising a dielectric layer between the first copper pad and the second copper pad, wherein the dielectric layer electrically isolates the first copper pad and the second copper pad from each other.
12. 12 . The substrate of claim 1 , further comprising a dielectric layer between the first side of the first glass layer and the side of the second glass layer.
13. 13 . The substrate of claim 12 , wherein the dielectric layer includes one or more electrically conductive features that electrically couple the first side of the first glass layer with the side of the second glass layer.
14. 14 . The substrate of claim 11 , wherein the dielectric layer includes a capacitor, the capacitor comprising: a first copper pad at a first side of the dielectric layer adjacent to the first glass layer; a second copper pad at a second side of the dielectric layer adjacent to the second glass layer; and wherein the first copper pad, the second copper pad, and a portion of the dielectric layer between the first copper pad and the second copper pad form the capacitor.
15. 15 . The substrate of claim 1 , wherein the one or more electrically conductive features are formed using blind vias in the side of the first glass layer or in the side of the second glass layer.
16. 16 . The substrate of claim 1 , wherein a side of the third glass layer includes one or more electrically conductive features; and wherein the side of the third glass layer is electrically and physically coupled with the second side of the first glass layer.
17. 17 . A substrate comprising: a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features; a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features; wherein the first side of the first glass layer is coupled with the side of the second glass layer; a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer, wherein the first side of the first glass layer includes a first copper pad with a surface that is substantially parallel to a plane of the first side of the first glass layer, wherein the side of the second glass layer includes a second copper pad with a surface that is substantially parallel to the plane of the first side of the first glass layer, and wherein the first copper pad and the second copper pad at least partially overlap each other with respect to a direction perpendicular to the plane of the first side of the first glass layer; and a dielectric layer between the first copper pad and the second copper pad, wherein the dielectric layer electrically isolates the first copper pad and the second copper pad from each other.
18. 18 . The substrate of claim 17 , wherein the dielectric layer includes a capacitor, the capacitor comprising: a first copper pad at a first side of the dielectric layer adjacent to the first glass layer; a second copper pad at a second side of the dielectric layer adjacent to the second glass layer; and wherein the first copper pad, the second copper pad, and a portion of the dielectric layer between the first copper pad and the second copper pad form the capacitor.
19. 19 . A substrate comprising: a first glass layer, wherein a first side of the first glass layer includes one or more electrically conductive features; a second glass layer, wherein a side of the second glass layer includes one or more electrically conductive features; wherein the first side of the first glass layer is coupled with the side of the second glass layer; a third glass layer coupled to a second side of the first glass layer, the second side of the glass layer opposite the first side of the first glass layer; and a dielectric layer between the first side of the first glass layer and the side of the second glass layer.
20. 20 . The substrate of claim 19 , wherein the dielectric layer includes one or more electrically conductive features that electrically couple the first side of the first glass layer with the side of the second glass layer.

Description

FIELD Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular package assemblies with multiple core layers. BACKGROUND Continued reduction in computing package sizes of mobile electronic devices such as smart phones and ultrabooks is a driving force behind increased yield and quality of semiconductor packages. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a cross section side view, a top-down view, and a perspective view of a glass layer that includes a plurality of electrically conductive features, in accordance with various embodiments. FIG. 2 shows a cross section side view of a package core that includes multiple glass layers that are bonded together and that include a plurality of electrically conductive features, in accordance with various embodiments. FIG. 3 shows cross section side views of package cores that includes multiple glass layers that are bonded together and that include a dielectric layer between glass layers, in accordance with various embodiments. FIG. 4 shows cross section side views of package cores with multiple build-up layers and dies attached to the build-up layers, in accordance with various embodiments. FIG. 5 illustrates multiple examples of laser-assisted etching of glass interconnects processes, in accordance with embodiments. FIG. 6 illustrates an example of a process for creating a multilayer glass core with conductive features, in accordance with various embodiments. FIG. 7 schematically illustrates a computing device, in accordance with various embodiments. DETAILED DESCRIPTION Embodiments of the present disclosure may generally relate to systems, apparatus, techniques, and/or processes directed to a package that include multiple glass layers within the package. In embodiments, a core of the package may include multiple glass layers that may be bonded together. In other embodiments, one or more of the multiple glass layers may be separated by a non-glass layer, such as a dielectric layer. In embodiments, the glass layers may include one or more electrically conductive features, such as conductive vias, conductive planes, electrical pads, electrical traces, redistribution layers, capacitors, inductors, active dies and/or passive dies. In embodiments, a glass layer may include one or more through glass vias, and/or blind vias that are etched into the glass using techniques described below. Legacy microelectronic packaging is dominated by multilayer organic packaging substrates within a package. Such substrates include multiple layers, which may be referred to as a stack, within one or more core layers. Signal communication within a package or between packages usually requires a path through the one or more core layers. In legacy implementations, a copper cladded laminate (CCL) core is used. While useful to improve substrate warpage, CCL implementations do not allow narrow drilling for high density plated through holes (PTH) to support high-bandwidth communication. Similarly, in legacy implementations it is difficult to integrate components within the CCL core or to fabricate packages with multilayer CCL core layers. Embodiments of packages that include multiple glass layers may include ultra-thin conductive traces within a core stack. Embodiments may also include integrated components such as inductors, capacitors, and the like between the glass layers or within the glass layers within the core stack. Embodiments that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers. In embodiments, using multiple glass layers within packages may also lead to increased performance versus legacy CCL core implementations. Techniques used to create narrow and/or high aspect ratio through glass vias (TGV), as well as to create trenches of various steps and sizes within glass, which may be referred to as blind vias, are described herein. These techniques may be used to fabricate packages and/or package cores that include multiple glass layers. These techniques may include laser-assisted glass etching allowing crack free, high-density via drills to be formed into a glass substrate. Different process parameters can be adjusted to achieve drills of various shapes and depths within glass. In embodiments, the results of these drills may be filled in with material other than a metal material like copper. It should be noted that glass layers may be processed by wafer, by panel, or by sub panel. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present di