US-12622288-B2 - Package substrate and/or a board with a shared power distribution network

Abstract

A device comprising a substrate, a first integrated device coupled to a first surface of the substrate, a second integrated device coupled to the first surface of the substrate, a first passive device coupled to a second surface of the substrate and a second passive device coupled to the second surface of the substrate. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects are configured to operate as an inductor, where the first plurality of interconnects include a via interconnect.

Inventors

• Lili Xu
• Jason Gonzalez

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260505

Application Date

20221116

Claims (20)

1. 1 . A device comprising: a substrate comprising: at least one dielectric layer; and a plurality of interconnects that are formed on at least a plurality of metal layers of the substrate, wherein the plurality of metal layers include a first metal layer and a second metal layer, wherein the plurality of interconnects include a first plurality of interconnects, a second plurality of interconnects and a power interconnect, wherein the second plurality of interconnects include pad interconnects that are configured to provide electrical paths for input/output signals, wherein the first plurality of interconnects and the power interconnect are configured to be electrically coupled to power, and wherein the power interconnect includes an interconnect that has a width that is greater than any width of all interconnects from the second plurality of interconnects; a first integrated device coupled to a first surface of the substrate; a second integrated device coupled to the first surface of the substrate; a first passive device coupled to the substrate; and a second passive device coupled to the substrate, wherein the first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through the first plurality of interconnects from the plurality of interconnects, and wherein at least one interconnect from the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to power, wherein the first plurality of interconnects include a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect.
2. 2 . The device of claim 1 , wherein the substrate includes a board substrate or a package substrate.
3. 3 . The device of claim 1 , wherein the first passive device is coupled to the first surface of the substrate, and wherein the second passive device is coupled to the first surface of the substrate.
4. 4 . The device of claim 1 , wherein the first passive device is coupled to a second surface of the substrate, and wherein the second passive device is coupled to the second surface of the substrate.
5. 5 . The device of claim 1 , wherein the first passive device is located in the substrate, and wherein the second passive device is located in the substrate.
6. 6 . The device of claim 1 , wherein the inductor is located along a common electrical path between the first integrated device, the second integrated device, the first passive device and the second passive device.
7. 7 . The device of claim 1 , wherein the first integrated device and the second integrated device are configured to share a common power supply.
8. 8 . The device of claim 7 , further comprising a power management integrated circuit (PMIC) configured to provide the common power supply for the first integrated device and the second integrated device.
9. 9 . The device of claim 1 , wherein the first passive device includes a first capacitor, and wherein the second passive device includes a second capacitor.
10. 10 . The device of claim 1 , wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
11. 11 . A device comprising: a board substrate comprising: at least one dielectric layer; and a plurality of interconnects that are formed on at least a plurality of metal layers of the board substrate, wherein the plurality of metal layers include a first metal layer and a second metal layer, wherein the plurality of interconnects include a first plurality of interconnects, a second plurality of interconnects and a power interconnect, wherein the second plurality of interconnects include pad interconnects that are configured to provide electrical paths for input/output signals, wherein the first plurality of interconnects and the power interconnect are configured to be electrically coupled to power, and wherein the power interconnect includes an interconnect that has a width that is greater than any width of all interconnects from the second plurality of interconnects; a first integrated device coupled to a first surface of the board substrate; a second integrated device coupled to the first surface of the board substrate; a first passive device coupled to a second surface of the board substrate; and a second passive device coupled to the second surface of the board substrate, wherein the first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through the first plurality of interconnects from the plurality of interconnects, and wherein the first plurality of interconnects are configured to operate as an inductor configured to be electrically coupled to power, wherein the first plurality of interconnects include a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect.
12. 12 . The device of claim 11 , wherein the first plurality of interconnects include a common electrical path between the first integrated device, the second integrated device, the first passive device and the second passive device, wherein the first plurality of interconnects include several interconnects on the first metal layer, several interconnects on the second metal layer and several via interconnects between the first metal layer and the second metal layer, and wherein the first plurality of interconnects define several windings of the inductor.
13. 13 . The device of claim 11 , wherein the first integrated device and the second integrated device share the power that is configured to be provided through the power interconnect.
14. 14 . The device of claim 11 , wherein the first metal layer is different from the second metal layer, and wherein the first metal layer may be any metal layer of the board substrate.
15. 15 . The device of claim 11 , wherein the first metal layer is different from the second metal layer, and wherein the second metal layer may be any metal layer of the board substrate.
16. 16 . The device of claim 11 , further comprising a power management integrated circuit coupled to the board substrate, wherein the power management integrated circuit is configured to be coupled to the inductor through the power interconnect.
17. 17 . The device of claim 11 , further comprising a ferrite bead device coupled to the board substrate.
18. 18 . The device of claim 11 , wherein the plurality of metal layers further include a third metal layer and a fourth metal layer, wherein the first plurality of interconnects include several interconnects on the first metal layer, several interconnects on the second metal layer, several via interconnects between the first metal layer and the second metal layer, several interconnects on the third metal layer, several via interconnects between the second metal layer and the third metal layer, several interconnects on the fourth metal layer, and several interconnects between the third metal layer and the fourth metal layer, and wherein the first plurality of interconnects define several windings of the inductor.
19. 19 . The device of claim 11 , wherein the second plurality of interconnects further include a plurality of trace interconnects configured to provide at least one electrical path for input/output signals, and wherein the power interconnect includes a width that is greater than any width of all trace interconnects for the plurality of trace interconnects configured to provide input/output signals.
20. 20 . The device of claim 19 , wherein the width of the power interconnect is at least 50 percent greater than the width of any trace interconnect of the plurality of trace interconnects.

Description

FIELD Various features relate to a board, a package and a substrate. BACKGROUND A package may include a substrate and integrated devices. These components are coupled together to provide a package that may perform various functions. The performance of a package and its components may depend on how power may be provided to the package and/or its components through a board. There is an ongoing need to provide packages with improved performances. SUMMARY Various features relate to a board, a package and a substrate. One example provides a device comprising a substrate, a first integrated device coupled to a first surface of the substrate, a second integrated device coupled to the first surface of the substrate, a first passive device coupled to the substrate and a second passive device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects that are formed on at least a plurality of metal layers of the substrate. The plurality of metal layers include a first metal layer and a second metal layer. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. At least one interconnect from the first plurality of interconnects is configured to operate as an inductor configured to be electrically coupled to power. The first plurality of interconnects include a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect. One example provides a device comprising a board substrate, a first integrated device coupled to a first surface of the board substrate, a second integrated device coupled to the first surface of the board substrate, a first passive device coupled to a second surface of the board substrate and a second passive device coupled to the second surface of the board substrate. The board substrate comprises at least one dielectric layer and a plurality of interconnects that are formed on at least a plurality of metal layers of the board substrate. The plurality of metal layers include a first metal layer and a second metal layer. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects are configured to operate as an inductor configured to be electrically coupled to power, where the first plurality of interconnects include a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect. One example provides a device comprising a package substrate, a first integrated device coupled to a first surface of the package substrate, a second integrated device coupled to the first surface of the package substrate, a first passive device coupled to a second surface of the package substrate and a second passive device coupled to the second surface of the package substrate. The package substrate comprises at least one dielectric layer and a plurality of interconnects that are formed on at least a plurality of metal layers of the package substrate. The plurality of metal layers include a first metal layer and a second metal layer. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects are configured to operate as an inductor configured to be electrically coupled to power, where the first plurality of interconnects include a first interconnect on the first metal layer, a second interconnect on the second metal layer, and a via interconnect coupled to the first interconnect and the second interconnect. BRIEF DESCRIPTION OF THE DRAWINGS Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. FIG. 1 illustrates a profile cross sectional view of integrated devices coupled to a board substrate. FIG. 2 illus