US-12622290-B2 - Chip structure and method of fabricating the same

US12622290B2US 12622290 B2US12622290 B2US 12622290B2US-12622290-B2

Abstract

A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.

Inventors

Kuo-Chiang Ting
Jian-Wei Hong
Sung-Feng Yeh

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260505
Application Date: 20230110

Claims (20)

1 . A chip structure, comprising: a bridge structure comprising an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure; and a dielectric fill disposed on the bridge structure and laterally surrounding the semiconductor dies, wherein a sidewall of the dielectric fill is coplanar to the sidewall of the bridge structure and the sidewall of the die support.
2 . The chip structure of claim 1 , wherein a top of the interconnect bridge is co-leveled with the top of the dielectric layer.
3 . The chip structure of claim 1 , wherein a bottom of the interconnect bridge is co-leveled with the bottom of the dielectric layer.
4 . The chip structure of claim 1 , wherein each of the semiconductor dies comprises a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a bonding structure disposed on the interconnect structure, and the boding structure comprises bonding conductors and a bonding dielectric surrounding the bonding conductors.
5 . The chip structure of claim 4 , wherein the bonding conductors and the bonding dielectric of the bonding structure are in contact with the bridge structure.
6 . The chip structure of claim 1 , wherein the bridge structure further comprises a bonding structure disposed on the interconnect bridge and the dielectric layer, the boding structure comprises bonding conductors and a bonding dielectric laterally surrounding the bonding conductors, and the bonding conductors and the bonding dielectric are in contact with the semiconductor dies.
7 . The chip structure of claim 1 , further comprising a redistribution circuitry structure disposed on the bridge structure, wherein the bridge structure is interposed between the semiconductor dies and the redistribution circuitry structure.
8 . The chip structure of claim 1 , wherein the dielectric fill is interposed between the bridge structure and the die support.
9 . A chip structure, comprising: a die support; semiconductor dies disposed on the die support, each of the semiconductor dies comprises a semiconductor substrate, an interconnect structure and a bonding structure, wherein the interconnect structure is connected between the semiconductor substrate and the bonding structure, the bonding structure comprises a bonding dielectric and bonding conductors embedded in the bonding dielectric; an interconnect bridge extending between the semiconductor dies and connected to the bonding structure of each of the semiconductor dies; a dielectric layer beside the interconnect bridge, wherein a bottom of the dielectric layer is co-leveled with a bottom of the interconnect bridge; a redistribution circuitry structure disposed on the bottom of the interconnect bridge and the bottom of the dielectric layer, wherein a sidewall of the die support, a sidewall of the dielectric layer and a sidewall of the redistribution circuitry structure are coplanar; and a dielectric fill laterally surrounding the semiconductor dies, wherein a sidewall of the dielectric fill is coplanar to the sidewall of the dielectric layer.
10 . The chip structure of claim 9 , wherein the interconnect bridge comprises interlayer dielectric layers and conductive wirings between the interlayer dielectric layers, and one of the interlayer dielectric layers is co-leveled with the bottom of the dielectric layer.
11 . The chip structure of claim 9 , wherein a thickness of the interconnect bridge is identical to a thickness of the dielectric layer.
12 . The chip structure of claim 9 , wherein the dielectric fill and the redistribution circuitry structure are disposed at opposite sides of the dielectric layer.
13 . The chip structure of claim 12 , wherein the dielectric fill is in contact with a sidewall of the bonding structure.
14 . The chip structure of claim 9 , wherein a sidewall of the semiconductor substrate, a sidewall of the interconnect structure, and a sidewall of the bonding structure are coplanar.
15 . A method of fabricating a chip structure, comprising: attaching a bridge die to a carrier, wherein the bridge die comprises a semiconductor substrate and an interconnect bridge formed on the semiconductor substrate; removing the semiconductor substrate to remain the interconnect bridge on the carrier; forming a dielectric layer on the carrier, wherein the dielectric layer is beside laterally surrounding the interconnect bridge; forming through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; connecting disposing semiconductor dies on the interconnect bridge and the dielectric layer, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias the interconnect bridge laterally extends between the semiconductor dies; attaching the semiconductor dies on a die support and removing the carrier, wherein the semiconductor dies are disposed between the die support and the bridge structure, and a sidewall of the die support is coplanar with a sidewall of the bridge structure; and forming a dielectric fill disposed on the bridge structure and laterally surrounding the semiconductor dies, wherein a sidewall of the dielectric fill is coplanar to the sidewall of the bridge structure and the sidewall of the die support.
16 . The method of claim 14 , wherein the dielectric layer is formed on the carrier by forming a dielectric material layer to cover the interconnect bridge and performing a planarization operation until the interconnect bridge is exposed.
17 . The method of claim 14 , further forming a redistribution circuitry structure on the interconnect bridge and the dielectric layer.
18 . The method of claim 14 , further performing a singulation operation, wherein a sidewall of the dielectric layer and the sidewall of the die support are coplanar.
19 . The method of claim 14 , wherein the semiconductor dies are bonded to the interconnect bridge through a bonding structure, and the bonding structure comprises a bonding dielectric and bonding conductors surrounded by the bonding dielectric.
20 . The method of claim 14 , further filling a gap between the semiconductor dies using the dielectric fill.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of U.S. provisional application Ser. No. 63/405,893, filed on Sep. 13, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged, in multi-chip modules, or in other types of packaging, for example. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. Multiple electronic components such as integrated circuit dies may also require to be packaged integrally, in some applications. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A through 1L schematically illustrate respective steps of fabricating a chip structure in accordance with some embodiments of the disclosure. FIG. 2 schematically illustrate a chip structure in accordance with some embodiments of the disclosure. FIG. 3 schematically illustrated a chip structure in accordance with some embodiments of the disclosure. FIG. 4 schematically illustrates a chip structure in accordance with some embodiments of the disclosure. FIGS. 5 to 7 schematically illustrate the relationship between semiconductor dies and bridge structure in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. Packages and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the packages are illustr