US-12622292-B2 - Two-sided interconnected embedded chip packaging structure and manufacturing method therefor

US12622292B2US 12622292 B2US12622292 B2US 12622292B2US-12622292-B2

Abstract

A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.

Inventors

Xianming Chen
Jindong FENG
Benxia Huang
Yejie HONG

Assignees

ZHUHAI ACCESS SEMICONDUCTOR CO., LTD

Dates

Publication Date: 20260505
Application Date: 20220930
Priority Date: 20211118

Claims (7)

1 . A two-sided interconnected embedded chip packaging structure, comprising: a first insulating layer comprising a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, the first chip being attached to the inside of the lower surface of the first insulating layer; and a second insulating layer comprising a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, wherein the first insulating layer is laminated on the second insulating layer in a manner of contacting each other, the first conductive wire layer being provided with a second conductive copper column layer which penetrating through the second insulating layer, the first conductive copper column layer being connected with the first conductive wire layer, and the heat radiation copper surface being connected with the reverse side of the first chip; further comprising a device placing hole frame penetrating through the first insulating layer and the second insulating layer, wherein a second chip is attached to the bottom of the device placing hole frame, an insulated packaging layer is formed in a gap between the second chip and the device placing hole frame, and the first chip and the second chip differ in thickness; wherein a second wire layer is disposed on the upper surface of the first insulating layer and a third wire layer is disposed on the lower surface of the second insulating layer, a terminal of the first chip is connected with the second wire layer, a terminal of the second chip is connected with the second wire layer or the third wire layer, the first conductive wire layer and the second wire layer are conducted and connected by the first conductive copper column layer, and the first conductive wire layer and the third wire layer are conducted and connected by the second conductive copper column layer.
2 . The two-sided interconnected embedded chip packaging structure of claim 1 , further comprising a first solder mask and a second solder mask respectively formed on the second wire layer and the third wire layer, a first metal surface treatment layer is disposed in the first solder mask, and a second metal surface treatment layer is disposed in the second solder mask.
3 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein each of the first chip and the second chip comprises at least one chip.
4 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein the first insulating layer and the second insulating layer comprise the same or different insulating materials.
5 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein an end of the first conductive copper column layer is flush with or higher than the first insulating layer, and an end of the second conductive copper column layer is flush with or higher than the second insulating layer.
6 . The two-sided interconnected embedded chip packaging structure of claim 1 , wherein each of the first conductive copper column layer and the second conductive copper column layer comprises at least one copper through hole column.
7 . The two-sided interconnected embedded chip packaging structure of claim 6 , wherein each of the first conductive copper column layer and the second conductive copper column layer comprises at least one copper through hole column with the same or different sectional sizes and/or shapes.

Description

CROSS REFERENCE TO RELATED APPLICATIONS AND CLAIM OF PRIORITY The present application claims the benefit of Chinese Patent Application No. 202111410151.0 filed on Nov. 18, 2021 at the Chinese Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety. BACKGROUND 1. Technical Field The present disclosure relates to a packaging structure of an electronic device, in particular to a two-sided interconnected embedded chip packaging (ECP) structure and a manufacturing method therefor. 2. Background of the Invention In order to meet the development demand of an electronic technology, an electronic product tends to be miniaturized, thereby promoting the process of high-density integration of a semiconductor integrated circuit. How to reasonably package devices such as a plurality of chips to achieve high functionalization and miniaturization has become an important research subject in the current semiconductor packaging industry. Meanwhile, in view of cost and efficiency, panel-level packaging has also become the current tendency. In a process that a substrate is fabricated, devices such as chips are embedded into the substrate, by which the output efficiency is increased while the packaging volume is effectively reduced, and meanwhile, the cost is greatly reduced than that of wafer-level packaging. Through continuous development and evolution, a panel-level embedded packaging technology has been applied more and more and has played a more and more important role in the field of semiconductor packaging. In the meantime, the panel-level embedded packaging technology has been also developed. In the field of current panel-level embedded packaging, the embedded packaging for the devices such as the plurality of chips has been possible, but it still has certain limitations. The embedded packaging for the devices such as the plurality of chips has been possible by using an existing panel-level embedded packaging solution such as a panel-level embedded packaging solution disclosed in the Chinese patent CN109686669A. As shown in FIG. 1, in the solution, firstly, an organic polymer frame 10 with a cavity is prefabricated by using a coreless copper column method; next, the plurality of devices 11 are embedded into the cavity of the polymer frame 10 at one time, and single-sided fanout is performed after packaging; and then, double-sided layer addition is performed. The solution has certain limitations that before the embedded packaging for the devices is performed, the polymer frame with the cavity needs to be prefabricated, so that the processing process is long, and the cost is high; the plurality of devices which are subjected to the embedded packaging are required to be disposed on the same layer so as to be small in designed degree of freedom, and the devices which are greater in thickness difference may not be packaged at the same time; and after the embedded packaging for the plurality of devices is completed, only single-sided fanout may be achieved, and therefore, the wiring difficulty is high. SUMMARY Implementation solutions of the present disclosure provide a two-sided interconnected embedded chip packaging structure and a manufacturing method therefor to solve the above-mentioned technical problems. According to the present disclosure, devices such as chips are attached to a copper plate on which copper columns have been predisposed, then, first packaging is performed, and a process of fabricating a frame is omitted, so that the cost is reduced; after the first packaging is completed, layers are added, and a cavity is fabricated; and second packaging is performed, the devices such as the chips are embedded to be packaged in the cavity, and fanout is performed after packaging is completed. By in-batch embedded packaging, the purpose of packaging the devices on different layers is achieved to meet the embedded packaging of the devices greatly differing in thickness. Meanwhile, by in-batch embedded packaging, two-sided fanout and interconnection of a plurality of devices may be achieved. A first aspect of the present disclosure relates to a manufacturing method for a two-sided interconnected embedded chip packaging structure, including the following steps: (a) preparing a copper plate, and forming a first conductive copper column layer and a first loopback strip-shaped copper column layer on the surface of at least one side of the copper plate, wherein the first loopback strip-shaped copper column layer includes at least one loopback strip-shaped copper column;(b) attaching a first chip to the surface of the copper plate, locating the first chip between adjacent first conductive copper columns of the first conductive copper column layer, and forming a first insulating layer on the surface of the copper plate to package the first conductive copper column layer, the first loopback strip-shaped copper column layer and the first chip;(c) etching the copper plate to for