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US-12622293-B2 - Semiconductor device

US12622293B2US 12622293 B2US12622293 B2US 12622293B2US-12622293-B2

Abstract

According to one embodiment, a semiconductor device is provided. The semiconductor device includes a first semiconductor module, a redistribution layer (RDL) module and a second semiconductor module. The RDL module is disposed on the first semiconductor module. The RDL module includes a plurality of polymer layers and a plurality of vias. The polymer layers are stacked on the first semiconductor module. The vias are disposed within the polymer layers. The second semiconductor module is disposed on the RDL module. A height difference of a top surface of at least one of the polymer layers ranges from 0 um to 1 um; or an angle between a sidewall and a bottom surface of at least one of the vias ranges from 90° to 95°; or a glass transition temperature (Tg) of at least one of the polymer layers is larger than 260° C.

Inventors

  • Meng-Che Tu
  • Po-Nan Yeh
  • Miao-Ken HUNG
  • Po-Han Wang
  • Yu-Hsiang Hu
  • Hung-Jui Kuo

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260505
Application Date
20230119

Claims (20)

  1. 1 . A semiconductor device, comprising: a first semiconductor module; a redistribution layer (RDL) module, disposed on the first semiconductor module, wherein the RDL module includes: a plurality of polymer layers, stacked on the first semiconductor module; and a plurality of vias, disposed within the polymer layers, wherein a height difference of a top surface of at least one of the polymer layers ranges from 0 μm to 1 μm; and a second semiconductor module, disposed on the RDL module; wherein a light transmittance of at least one of the polymer layers for a light with a wavelength ranging from 500 nm to 700 nm is larger than 95%.
  2. 2 . The semiconductor device according to claim 1 , wherein an angle between a sidewall and a bottom surface of at least one of the vias ranges from 90° to 95°.
  3. 3 . The semiconductor device according to claim 1 , wherein a glass transition temperature (Tg) of at least one of the polymer layers is larger than 260° C.
  4. 4 . The semiconductor device according to claim 1 , wherein at least one of the polymer layers includes 10% to 20% of polyimide and 0% to 0.5% of epoxy.
  5. 5 . The semiconductor device according to claim 1 , wherein compositions of at least two of the polymer layers are different.
  6. 6 . The semiconductor device according to claim 1 , wherein at least one of the polymer layers includes 10% to 20% of polyimide and 0% to 0.5% of epoxy and one of the polymer layers includes 25% to 35% of polyimide and 0% to 5% of crosslinked material.
  7. 7 . The semiconductor device according to claim 1 , wherein at least two of the vias are stacked to form a pillar, a top of the pillar is covered by one of the polymer layers whose bottom surface is substantially flat.
  8. 8 . The semiconductor device according to claim 1 , wherein the polymer layers have different glass transition temperatures.
  9. 9 . A semiconductor device, comprising: a first semiconductor module; a redistribution layer (RDL) module, disposed on the first semiconductor module, wherein the RDL module includes: a plurality of polymer layers, stacked on the first semiconductor module; and a plurality of vias, disposed within the polymer layers, wherein an angle between a sidewall and a bottom surface of at least one of the vias ranges from 90° to 95°; and a second semiconductor module, disposed on the RDL module; wherein at least one of the polymer layers includes 10% to 20% of polyimide and 0% to 0.5% of epoxy and one of the polymer layers includes 25% to 35% of polyimide and 0% to 5% of crosslinked material.
  10. 10 . The semiconductor device according to claim 9 , wherein a glass transition temperature (Tg) of at least one of the polymer layers is larger than 260° C.
  11. 11 . The semiconductor device according to claim 9 , wherein a light transmittance of at least one of the polymer layers for a light whose wavelength ranges from 500 nm to 700 nm is larger 95%.
  12. 12 . The semiconductor device according to claim 9 , wherein at least one of the polymer layers includes 10% to 20% of polyimide and 0% to 0.5% of epoxy.
  13. 13 . The semiconductor device according to claim 9 , wherein materials of at least two of the polymer layers are different.
  14. 14 . The semiconductor device according to claim 9 , wherein at least two of the vias are stacked to form a pillar, a top of the pillar is cover one of the polymer layers whose bottom surface is substantially flat.
  15. 15 . The semiconductor device according to claim 9 , wherein the polymer layers have different glass transition temperatures.
  16. 16 . A semiconductor device, comprising: a first semiconductor module; a redistribution layer (RDL) module, disposed on the first semiconductor module, wherein the RDL module includes: a plurality of polymer layers, stacked on the first semiconductor module; and a plurality of vias, disposed within the polymer layers, wherein a glass transition temperature (Tg) of at least one of the polymer layers is larger than 260° C.; and a second semiconductor module, disposed on the RDL module; wherein a light transmittance of at least one of the polymer layers for a light with a wavelength ranging from 500 nm to 700 nm is larger than 95%.
  17. 17 . The semiconductor device according to claim 16 , wherein at least one of the polymer layers includes 10% to 20% of polyimide and 0% to 0.5% of epoxy.
  18. 18 . The semiconductor device according to claim 16 , wherein materials of at least two of the polymer layers are different.
  19. 19 . The semiconductor device according to claim 16 , wherein at least two of the vias are stacked to form a pillar, a top of the pillar is covered by one of the polymer layers whose bottom surface is substantially flat.
  20. 20 . The semiconductor device according to claim 16 , wherein the polymer layers have different glass transition temperatures.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of U.S. provisional application Ser. No. 63/429,304, filed Dec. 1, 2022, the subject matter of which is incorporated herein by reference. BACKGROUND The disclosure relates in general to a semiconductor device, and more particularly to a semiconductor device having polymer layers. With the development of semiconductor technology, more than two semiconductor modules may be integrated via advanced packaging technologies. For example, a plurality of conductive traces embedded in polymers are used to connect the semiconductor modules. However, the advanced packaging technology often suffers a polymer delamination issue. After some high temperature process, such as annealing or curing, the polymer might be separated from the metal traces. The researchers are trying to solve this problem. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 shows a semiconductor device according to one embodiment. FIG. 2 shows a deformation curve of one polymer layer having low glass transition temperature. FIG. 3 shows a deformation curve of one polymer layer having high glass transition temperature. FIG. 4 illustrates one characteristic of the semiconductor device. FIG. 5 illustrates another characteristic of the semiconductor device. FIG. 6 illustrates another characteristic of the semiconductor device. FIG. 7 illustrates another characteristic of the semiconductor device. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Please refer to FIG. 1, which shows a semiconductor device 100 according to one embodiment. The semiconductor device 100 includes a first semiconductor module 110, a second semiconductor module 120 and a redistribution layer (RDL) module 130. The first semiconductor module 110 is, for example, a chip or a memory. The second semiconductor module 120 is, for example, a package, a chip, a memory or a substrate. The RDL module 130 is used to fan out the traces for integrating the first semiconductor module 110 and the second semiconductor module 120. As shown in FIG. 1, the RDL module 130 is disposed on the first semiconductor module 110. For example, the RDL module 130 could be bonded with the first semiconductor module 110 through copper bumps. Or, the RDL module 130 could be directly formed on the first semiconductor module 110 in way of layer by layer. The second semiconductor module 120 is disposed on the RDL module 130. The second semiconductor module 120 could be bonded with the RDL module 130. Or, the second semiconductor module 120 could be jointed with the RDL module 130 through solder balls. The RDL module 130 includes, for example, a plurality of polymer layers PM0, PM1, PM2, PM3, PM4, PM5, a plurality of vias VA1, VA2, VA3, VA4 and a plurality of traces TR1, TR2, TR3, TR4. The polymer layers PM0, PM1, PM2, PM3, PM4, PM5 are stacked on the first semiconductor module 110. The vias VA1, VA2, VA3, VA4 are disposed within the polymer layers PM0, PM1, PM2, PM3, PM4, PM5. The vias VA1, VA2, VA3 are stacked to form a pillar PL. Please refer to FIG. 2, which