US-12622294-B2 - Methods and apparatus to improve signal integrity performance in integrated circuit packages

Abstract

Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed. An integrated circuit (IC) package includes a substrate; a first conductive pad in a first metal layer in the substrate; and a second conductive pad in a second metal layer in the substrate. The first metal layer is adjacent the second metal layer with no intervening metal layers therebetween. The integrated circuit (IC) package further includes a conductive protrusion extending from the first conductive pad toward the second conductive pad.

Inventors

• Cemil Geyik
• Kemal Aygun
• Yidnekachew Mekonnen
• Zhichao Zhang
• Suddhasattwa NAD

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220429

Claims (20)

1. 1 . An integrated circuit (IC) package comprising: a substrate including an array of contacts on a first surface of the substrate, the contacts associated with metal in a base metal layer of the substrate; a first conductive pad in a first metal layer in the substrate; a second conductive pad in a second metal layer in the substrate, the first metal layer adjacent the second metal layer with no intervening metal layers therebetween, the base metal layer different than the first metal layer and different than the second metal layer; and a conductive protrusion extending from the first conductive pad toward the second conductive pad.
2. 2 . The IC package of claim 1 , wherein the conductive protrusion is electrically connected to a first contact in the array of contacts.
3. 3 . The IC package of claim 2 , wherein the first metal layer corresponds to the base metal layer, the first conductive pad corresponds to the first contact, and the second metal layer corresponds to a base-1 metal layer of the substrate.
4. 4 . The IC package of claim 2 , wherein the second metal layer corresponds to the base metal layer, the second conductive pad corresponds to the first contact, and the first metal layer corresponds to a base-1 metal layer of the substrate.
5. 5 . The IC package of claim 2 , wherein the array of contacts corresponds to a land grid array.
6. 6 . The IC package of claim 2 , wherein the array of contacts corresponds to a ball grid array.
7. 7 . The IC package of claim 1 , wherein one of the first conductive pad or the second conductive pad corresponds to a ground plane in the substrate.
8. 8 . The IC package of claim 1 , wherein the first conductive pad is associated with a conductive arm electrically connected to a first contact on the substrate, the conductive arm extending along the first metal layer away from the first contact and toward a second contact, the second conductive pad associated with the second contact.
9. 9 . The IC package of claim 8 , wherein the conductive arm is a stub having a distal end that is spaced apart from a path for an electrical signal transmitted through the first contact.
10. 10 . The IC package of claim 8 , wherein the conductive arm defines a portion of a path for an electrical signal transmitted through the first contact.
11. 11 . The IC package of claim 1 , wherein the substrate is a package substrate of the IC package, the package substrate exposed to an exterior of the IC package.
12. 12 . The IC package of claim 1 , wherein the substrate is an interposer disposed within the IC package, the interposer mounted to a separate package substrate of the IC package.
13. 13 . The IC package of claim 1 , wherein the conductive protrusion extends from the first conductive pad to the second conductive pad at least 25% of a distance between the first and second metal layers.
14. 14 . An apparatus comprising: a substrate including a first surface and a second surface opposite the first surface; an array of contacts on the first surface of the substrate; a semiconductor die mounted on the second surface of the substrate, the contacts associated with signal paths through the substrate to electrically couple the semiconductor die with the contacts; a first conductive pad electrically connected to a first signal path of the signal paths, the first conductive pad electrically connected to a first contact of the array of contacts through a conductive arm extending away from the first contact, the conductive arm electrically connected to the first contact through a metal via in a via stack electrically connected to the first contact, the via stack defining the first signal path; and a second conductive pad electrically connected to a second signal path of the signal paths, the second signal path different than the first signal path, a distance between the first and second conductive pads being less than a distance between adjacent metal layers in the substrate.
15. 15 . The apparatus of claim 14 , wherein at least one of the first conductive pad or the second conductive pad corresponds to one of the contacts.
16. 16 . The apparatus of claim 14 , wherein the conductive arm is electrically connected to the first contact independent of a via stack electrically connected to the first contact, the via stack defining the first signal path.
17. 17 . The apparatus of claim 14 , wherein the first and second conductive pads are positioned to reduce crosstalk between the first and second signal paths.
18. 18 . An apparatus, comprising: a package substrate; a plurality of metal layers within the package substrate, the metal layers including metal defining metal interconnects through the package substrate; a plurality of dielectric layers, different ones of the dielectric layers between adjacent ones of the metal layers; and a metal plate between first metal in a first metal layer and second metal in a second metal layer, the first and second metal layers adjacent one another, the metal plate in contact with the first metal.
19. 19 . The apparatus of claim 18 , wherein the first metal is electrically connected to a first one of the metal interconnects and the second metal is electrically connected to a second one of the metal interconnects.
20. 20 . The apparatus of claim 18 , wherein the metal plate is an integral extension of the first metal.

Description

FIELD OF THE DISCLOSURE This disclosure relates generally to integrated circuits and, more particularly, to methods and apparatus to improve signal integrity performance in integrated circuit packages. BACKGROUND In many integrated circuit packages, one or more semiconductor dies are mechanically and electrically coupled to an underlying package substrate. Many such package substrates include an array of contacts (e.g., a ball grid array (BGA), a land grid array (LGA), or a pin grid array (PGA)) to enable the package to be mechanically and electrically coupled to a printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example integrated circuit (IC) package constructed in accordance with teachings disclosed herein. FIGS. 2-4 illustrate a portion of an example package substrate constructed in accordance with teachings disclosed here. FIGS. 5-7 illustrate a portion of another example package substrate constructed in accordance with teachings disclosed here. FIGS. 8-10 illustrate a portion of another example package substrate constructed in accordance with teachings disclosed here. FIG. 11 illustrate a portion of another example package substrate constructed in accordance with teachings disclosed here. FIG. 12 illustrate a portion of another example package substrate constructed in accordance with teachings disclosed here. FIG. 13 illustrate a portion of another example package substrate constructed in accordance with teachings disclosed here. FIGS. 14-17 illustrate stages in an example fabrication process to manufacture the example package substrate of FIGS. 2-4. FIGS. 18-21 illustrate stages in an example fabrication process to manufacture the example package substrate of FIGS. 5-7. FIG. 22 is a top view of a wafer and dies that may be included in an IC package constructed in accordance with teachings disclosed herein. FIG. 23 is a cross-sectional side view of an IC device that may be included in an IC package constructed in accordance with teachings disclosed herein. FIG. 24 is a cross-sectional side view of an IC device assembly that may include an IC package constructed in accordance with teachings disclosed herein. FIG. 25 is a block diagram of an example electrical device that may include an IC package constructed in accordance with teachings disclosed herein. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular. As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another. Notwithstanding the foregoing, in the case of a semiconductor device, “above” is not with reference to Earth, but instead is with reference to a bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) on which components of an integrated circuit are formed. Specifically, as used herein, a first component of an integrated circuit is “above” a second component when the first component is farther away from the bulk region of the semiconductor substrate than the second component. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts. Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imp