US-12622300-B1 - Method of assembling partitioned organic substrate in a flip chip package

Abstract

An integrated circuit (IC) package comprises: at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to corresponding terminals of an integrated circuit component and ii) to corresponding terminals of an interposer or a printed circuit board; at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units; and, an integrated circuit having terminals and configured to electrically couple to terminals of the substrate formed of at least two substrate sub-units.

Inventors

• Manish Nayini
• Janak G. Patel
• Richard S Graf

Assignees

• MARVELL ASIA PTE LTD

Dates

Publication Date

20260505

Application Date

20221115

Claims (10)

1. 1 . An integrated circuit (IC) package, comprising: an integrated circuit device having first terminals; at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to one or more of the first terminals of the integrated circuit device and ii) to second terminals of an interposer or a printed circuit board; and at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units, wherein the integrated circuit device is configured to electrically couple via the first terminals to third terminals of the substrate formed of the at least two substrate sub-units.
2. 2 . The IC package of claim 1 , wherein the at least one coupler is configured to join the at least two substrate sub-units at a substantially uniform distance from each other, and to electrically isolate the at least two substrate sub-units from each other.
3. 3 . The IC package of claim 1 , wherein the at least one coupler comprises at least one stabilizing bar configured to be placed between first and second substrate sub-units among the at least two of the substrate sub-units, and to connect the first and second substrate sub-units and align the first and second substrate sub-units to a common plane.
4. 4 . The IC package of claim 1 , wherein the at least one coupler comprises at least one stabilizing ring configured to: be placed over the at least two substrate sub-units, connect the at least two substrate sub-units, and align the at least two substrate sub-units to a common plane.
5. 5 . The IC package of claim 1 , wherein the at least one coupler is made of an electrically insulating material.
6. 6 . The IC package of claim 1 , wherein the at least one coupler comprises at least one circuit layer that is disposed over at least a portion of each of the at least two substrate sub-units, the circuit layer configured to connect the at least two substrate sub-units and align the at least two substrate sub-units to a common plane.
7. 7 . The IC package of claim 6 , wherein the at least one circuit layer comprises one of (i) a solder-mask layer and (ii) a dummy redistribution layer (RDL).
8. 8 . The IC package of claim 1 , wherein the at least two substrate sub-units comprise a first substrate sub-unit and a second substrate sub-unit, and wherein the at least one coupler includes a mechanical interface on the first substrate sub-unit, the mechanical interface being configured to connect to a mating mechanical interface on the second substrate sub-unit.
9. 9 . The IC package of claim 8 , wherein the mechanical interface and the mating mechanical interface are configured to connect to one another by a male-female fit.
10. 10 . The IC package of claim 8 , wherein the mechanical interface and the mating mechanical interface are configured to connect to one another by a tongue and groove fit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of commonly owned U.S. Provisional Patent Application 63/279,992, entitled: Method of Assembling Partitioned Organic Substrate in a Flip Chip Package, filed Nov. 16, 2021, whose disclosure is incorporated herein in its entirety by reference. FIELD OF THE DISCLOSURE The present disclosure relates generally to organic package substrates for integrated circuits (IC), and particularly to methods and systems for producing organic substrates for use, for example, in flip chip IC packages. BACKGROUND As technology advances, the need for processing capacity of semiconductor chips and devices increases. Correspondingly, package sizes for chips are getting larger, to handle the increased processing demands. The chips are mounted to organic substrates, whose increasing size results in exponentially increasing material costs, due to yield issues at the panel level. Additionally, should a large organic substrate fail in pre-assembly tests, it must be rejected. This rejection is a financial loss for the manufacturer, as valuable material and in many instances, scarce material, is wasted. The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application. SUMMARY The present disclosure suggests replacing a single piece large organic substrate for integrated circuit (IC) packaging by multiple smaller substrate sub-units. The sub-units typically are combined prior to or during package assembly. This use of smaller units coupled with combining the units before or during package assembly, provides the combined substrate with the ability to maintain a total number of electrical connections, such as IC bumps and ball grid arrays (BGAs), as the equivalent single piece large organic substrate with multiple smaller units, providing substantial cost savings from use of the smaller units. The disclosed subject matter is directed to an integrated circuit (IC) package. The IC package comprises: at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to corresponding terminals of an integrated circuit component and ii) to corresponding terminals of an interposer or a printed circuit board; at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units; and, an integrated circuit having terminals and configured to electrically couple to terminals of the substrate formed of at least two substrate sub-units. Optionally, the IC package is such that the at least one coupler is configured to join the substrate sub-units at a substantially uniform distance from each other, and to electrically isolate the substrate sub-units from each other. Optionally, the IC package is such that wherein the at least one coupler comprises at least one stabilizing bar configured to be placed between two of the substrate sub-units, and to connect the two of the substrate sub-units and align the two of the substrate sub-units to a common plane. Optionally, the IC package is such that the at least one coupler comprises at least one stabilizing ring configured to be placed over at least two of the substrate sub-units, and to connect the at least two of the substrate sub-units and to align the at least two of the substrate sub-units to a common plane. Optionally, the IC package is such that the at least one coupler is made of an electrically insulating material. Optionally, the IC package is such that the at least one coupler comprises at least one circuit layer that is disposed over least a portion of each of the substrate sub-units, the circuit layer configured to connect the substrate sub-units and align the substrate sub-units to a common plane. Optionally, the IC package is such that the circuit layer comprises one of (i) a solder-mask layer and (ii) a dummy redistribution layer (RDL). Optionally, the IC package is such that the at least one coupler includes a mechanical interface on a first substrate sub-unit configured to connect to a mating mechanical interface on a substrate sub-unit, among the substrate sub-units. Optionally, the IC package is such that the mechanical interface and the mating mechanical interface are configured to connect to one another by a male-female fit. Optionally, the IC package is such that the mechanical interface and the mating mechanical interface are configured to connect to one another by a tongue and groove fit. The disclosed subject matter is directed to a method for producing an integrated circuit (IC) package. The method comprises: providing at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrica