US-12622302-B2 - Semiconductor package including a lower substrate and an upper substrate

US12622302B2US 12622302 B2US12622302 B2US 12622302B2US-12622302-B2

Abstract

A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.

Inventors

ChoongBin YIM
JongBo Shim
Jihwang Kim

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20220407
Priority Date: 20210719

Claims (19)

1 . A semiconductor package comprising: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the upper wiring layer is disposed on the core layer, wherein the plurality of dummy structures are respectively disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers at least a portion of the upper wiring layer and extends in the through-holes and on the plurality of dummy structures; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate and electrically connected to the lower wiring layer.
2 . The semiconductor package of claim 1 , wherein the plurality of dummy structures are arranged in rows and columns and are disposed inside the upper substrate.
3 . The semiconductor package of claim 1 , wherein a first plurality of dummy structures of the plurality of dummy structures are disposed to not overlap the semiconductor chip.
4 . The semiconductor package of claim 1 , wherein the semiconductor chip includes a hot spot having a heating value in a plane area thereof, and at least one of the plurality of dummy structures is disposed to overlap the hot spot of the semiconductor chip.
5 . The semiconductor package of claim 1 , wherein the solder resist layer has an opening exposing at least a portion of the upper wiring layer.
6 . The semiconductor package of claim 1 , wherein the plurality of dummy structures have a thickness greater than a thickness of the upper wiring layer.
7 . The semiconductor package of claim 1 , wherein the plurality of dummy structures have a thickness ranging from about 50 μm to about 100 μm in a first direction that is perpendicular to an upper surface of the semiconductor chip.
8 . The semiconductor package of claim 7 , wherein the plurality of dummy structures have a width ranging from about 0.1 mm to about 2 mm in a second direction crossing the first direction.
9 . The semiconductor package of claim 1 , wherein the lower substrate has a first coefficient of thermal expansion (CTE), wherein the upper substrate has a second CTE, and wherein the plurality of dummy structures have a third CTE smaller than each of the first and second coefficients of thermal expansion.
10 . The semiconductor package of claim 9 , wherein a difference between the first CTE and the second CTE is about 10 ppm/° C. due to the plurality of dummy structures.
11 . The semiconductor package of claim 9 , wherein the third CTE of the plurality of dummy structures ranges from about 1 ppm/° C. to about 20 ppm/° C.
12 . The semiconductor package of claim 1 , wherein the lower substrate, the semiconductor chip, and the upper substrate are stacked on each other in a first direction, the lower substrate has a first thickness in the first direction, and the upper substrate has a second thickness less than the first thickness in the first direction.
13 . The semiconductor package of claim 1 , wherein the lower wiring layer is provided as a plurality of lower wiring layers disposed on different levels from each other, the upper wiring layer is provided as a plurality of upper wiring layers disposed on different levels from each other, and a number of the plurality of upper wiring layers is less than a number of the plurality of lower wiring layers.
14 . A semiconductor package comprising: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including an insulating layer, an upper wiring layer, and a plurality of dummy structures, wherein the upper wiring layer is disposed on the insulating layer, and the plurality of dummy structures is electrically insulated from the upper wiring layer; and connection structures disposed to be adjacent to the semiconductor chip disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other, wherein a first plurality of dummy structures of the plurality of dummy structures are disposed in a position overlapping the semiconductor chip and a second plurality of dummy structures of the plurality of dummy structures are disposed to not overlap the semiconductor chip.
15 . The semiconductor package of claim 14 , wherein the plurality of dummy structures include a silicon (Si) dummy, the upper substrate includes a solder resist layer disposed on the insulating layer and exposing at least a portion of the upper wiring layer, and the plurality of dummy structures are covered by the solder resist layer.
16 . The semiconductor package of claim 14 , wherein the upper substrate includes a solder resist layer disposed on the insulating layer and exposing at least a portion of the upper wiring layer, and the plurality of dummy structures are attached to the solder resist layer.
17 . The semiconductor package of claim 14 , wherein the upper substrate includes a solder resist layer disposed on the insulating layer and at least partially surrounding upper portions of the connection structures, and the solder resist layer has a cavity overlapping the semiconductor chip.
18 . The semiconductor package of claim 17 , wherein the cavity has a width greater than a width of the semiconductor chip.
19 . A semiconductor package comprising: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including an insulating layer and an upper wiring layer disposed on the insulating layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer to the upper wiring layer; and a dummy structure embedded in the insulating layer of the upper substrate, wherein the dummy structure includes a passive element including a silicon chip electrically connected to the upper wiring layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 USC 119(a) to Korean Patent Application No. 10-2021-0094046 filed on Jul. 19, 2021 in the Korean Intellectual Property Office, the disclosure of Which is incorporated by reference herein in its entirety. TECHNICAL FIELD The present inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a lower substrate and an upper substrate. DISCUSSION OF THE RELATED ART Package-on-package (POP) technology of vertically stacking two or more semiconductor packages has been under development in accordance with trends in performance and miniaturization of electronic devices. In the case of a POP structure using an interposer substrate, technological developments for controlling warpage of a lower package are currently under development. SUMMARY According to an exemplary embodiment of the present inventive concept, a semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, Wherein the core layer has through-holes, wherein the upper wiring layer is disposed on the core layer, wherein the plurality of dummy structures are respectively disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers at least a portion of the upper wiring layer and extends in the through-holes and on the plurality of dummy structures; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate and electrically connected to the lower wiring layer. According to an exemplary embodiment of the present inventive concept, a semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including an insulating layer, an upper wiring layer, and a plurality of dummy structures, herein the upper wiring layer is disposed on the insulating layer, and the plurality of dummy structures is electrically insulated from the upper wiring layer; and connection structures disposed to be adjacent to the semiconductor chip disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other, wherein a first plurality of dummy structures of the plurality of dummy structures are disposed in a position overlapping the semiconductor chip and a second plurality of dummy structures of the plurality of dummy structures are disposed to not overlap the semiconductor chip. According to an exemplary embodiment of the present inventive concept, a semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including an insulating layer and an upper wiring layer disposed on the insulating layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer to the upper wiring layer; and a dummy structure embedded in the insulatinglayer of the upper substrate. BRIEF DESCRIPTION OF DRAWINGS The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof, with reference to the accompanying drawings, in which: FIG. 1A is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept, and FIG. 1B is a plan view illustrating a lower surface of an upper substrate taken along line I1-I1′ of FIG. 1A; FIG. 2 is a graph illustrating a change in warpage of a semiconductor package according to the presence or absence of a dummy structure; FIG. 3 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept; FIG. 4 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept; FIG. 5A is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept, and FIG. 5B is a plan view illustrating a low