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US-12622303-B2 - Notched wafer and bonding support structure to improve wafer stacking

US12622303B2US 12622303 B2US12622303 B2US 12622303B2US-12622303-B2

Abstract

Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.

Inventors

  • Sheng-Chan Li
  • Cheng-Hsien Chou
  • Sheng-Chau Chen
  • Cheng-Yuan Tsai

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260505
Application Date
20230503

Claims (20)

  1. 1 . A processing tool comprising: a housing structure defining a chamber; a first plate disposed in the chamber; a first plasma exclusion zone (PEZ) ring disposed on the first plate; a second plate disposed in the chamber and underlying the first plate; and a second PEZ ring disposed on the second plate, wherein the second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring, wherein a height of the PEZ ring notch is equal to a height of the second PEZ ring.
  2. 2 . The processing tool of claim 1 , wherein the processing tool comprises a wafer chuck configured to hold a semiconductor substrate comprising a substrate notch that extends inwardly from a circumferential edge of the semiconductor substrate, wherein the PEZ ring notch directly underlies the substrate notch.
  3. 3 . The processing tool of claim 2 , wherein the PEZ ring notch and the substrate notch comprise a same shape, wherein a size of the PEZ ring notch is greater than a size of the substrate notch.
  4. 4 . The processing tool of claim 1 , wherein outer sidewalls of the first PEZ ring are spaced laterally between outer sidewalls of the second PEZ ring.
  5. 5 . The processing tool of claim 1 , wherein the first PEZ ring comprises a bottom surface and an upper surface that is spaced vertically above the bottom surface of the first PEZ ring, wherein a height of the first PEZ ring continuously decreases from the bottom surface of the first PEZ ring to the upper surface of the first PEZ ring.
  6. 6 . The processing tool of claim 1 , wherein a distance between the PEZ ring notch and a circumferential edge of the second plate is less than a width of the PEZ ring notch.
  7. 7 . The processing tool of claim 1 , wherein the first PEZ ring and the second PEZ ring respectively comprise yttrium oxide.
  8. 8 . The processing tool of claim 1 , wherein the height of the second PEZ ring discretely decreases from an inner surface of the second PEZ ring to an outer surface of the second PEZ ring in a direction towards the outer surface of the second PEZ ring.
  9. 9 . The processing tool of claim 1 , wherein the first PEZ ring has a continuous ring shape that is devoid of a notch extending inwardly from the circumferential edge of the first PEZ ring.
  10. 10 . A processing tool comprising: a housing structure; and a plate structure disposed within the housing structure and comprising a plasma exclusion zone (PEZ) ring laterally enclosing a plate, wherein the PEZ ring comprises one or more surfaces defining a PEZ notch disposed at an outer region of the plate structure, wherein the PEZ notch underlies a substrate notch of a semiconductor substrate disposed in the housing structure, wherein the one or more surfaces comprise a first sidewall segment adjacent to an outer perimeter of the PEZ ring and a second sidewall segment adjacent to the outer perimeter of the PEZ ring, wherein the first sidewall segment is laterally offset from the second sidewall segment by a lateral distance, wherein the PEZ ring is discontinuous across the lateral distance.
  11. 11 . The processing tool of claim 10 , wherein the processing tool is configured to flow one or more processing gas(es) into the housing structure while the substrate notch overlies the PEZ notch such that the one or more processing gas(es) is or are directed towards the substrate notch.
  12. 12 . The processing tool of claim 11 , wherein the processing tool is configured to deposit a dielectric structure along the substrate notch while flowing the one or more processing gas(es).
  13. 13 . The processing tool of claim 12 , wherein the dielectric structure comprises a notch extending inwardly from a circumferential edge of the dielectric structure, wherein the notch of the dielectric structure conforms to a shape of the PEZ notch.
  14. 14 . The processing tool of claim 10 , wherein the one or more surfaces of the PEZ ring comprise a first planar surface and a second planar surface that meet at a point, wherein the first sidewall segment is part of the first planar surface and the second sidewall segment is part of the second planar surface, wherein heights of the first and second sidewall segments are less than a height of the PEZ ring at the point.
  15. 15 . The processing tool of claim 10 , wherein the one or more surfaces of the PEZ ring comprise a curved surface laterally offset from the first and second sidewall segments.
  16. 16 . A processing tool comprising: a housing structure; an upper plate structure disposed within the housing structure and comprising an upper plasma exclusion zone (PEZ) ring disposed around an outer perimeter of an upper plate; and a lower plate structure disposed within the housing structure and underlying the upper plate structure, wherein the lower plate structure comprises a lower PEZ ring laterally disposed around an outer perimeter of a lower plate, wherein the lower PEZ ring comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring, wherein the PEZ ring notch continuously vertically extends from a top surface of the lower PEZ ring to a bottom surface of the lower PEZ ring.
  17. 17 . The processing tool of claim 16 , wherein a width of the lower PEZ ring is greater than a width of the upper PEZ ring.
  18. 18 . The processing tool of claim 16 , wherein a size of the lower plate structure is greater than a size of the upper plate structure.
  19. 19 . The processing tool of claim 16 , wherein the lower PEZ ring comprises an inner region having a first height and an outer region having a second height less than the first height, wherein a width of the inner region of the lower PEZ ring is greater than a width of the upper PEZ ring.
  20. 20 . The processing tool of claim 19 , wherein the second height is less than a height of the lower plate.

Description

REFERENCE TO RELATED APPLICATION This Application is a Divisional of U.S. application Ser. No. 17/197,254, filed on Mar. 10, 2021, the contents of which are hereby incorporated by reference in their entirety. BACKGROUND The semiconductor industry has continually improved the processing capabilities and power consumption of integrated circuits (ICs) by shrinking the minimum feature size. However, in recent years, process limitations have made it difficult to continue shrinking the minimum feature size. The stacking of two-dimensional (2D) ICs into three-dimensional (3D) ICs has emerged as a potential approach to continue improving processing capabilities and power consumption of ICs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A illustrates some embodiments of a top view of an integrated chip including a plurality of two-dimensional (2D) integrated circuits (ICs) overlying a semiconductor wafer with a notch and a bonding support structure surrounding a circumferential edge of the semiconductor wafer and extending continuously along the notch. FIG. 1B illustrates some embodiments of a top view of a portion of the semiconductor wafer and the bonding support structure of FIG. 1A. FIGS. 2A-C illustrate a cross-sectional view and top views of some embodiments of a semiconductor wafer and a processing tool having an upper plasma exclusion zone (PEZ) ring and a lower PEZ ring that comprises a PEZ ring notch. FIGS. 3A-3C illustrate cross-sectional views of some embodiments of a first semiconductor wafer bonded to a second semiconductor wafer, each having a bonding support structure disposed along a peripheral region. FIGS. 4A-B illustrate some embodiments of a cross-sectional view and a top view, respectively, of some more detailed embodiments of at least one of the semiconductor wafers of FIGS. 3A-C. FIGS. 5-17 illustrate cross-sectional views of some embodiments of a method of forming bonding support structures along and/or over notches of a first semiconductor wafer and a second semiconductor wafer, respectively, and bonding the first semiconductor wafer to the second semiconductor wafer. FIG. 18 illustrates a methodology in flowchart format that illustrates some embodiments of forming bonding support structures along and/or over notches of a first semiconductor wafer and a second semiconductor wafer, respectively, and bonding the first semiconductor wafer to the second semiconductor wafer. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Moreover, “first”, “second”, “third”, etc. may be used herein for ease of description to distinguish between different elements of a figure or a series of figures. “first”, “second”, “third”, etc. are not intended to be descriptive of the corresponding element, but rather are merely generic identifiers. For example, “a first dielectric layer” described in connection with a first figure may not necessarily correspond to a “first dielectric layer” described in connection with some embodiments, but rather may correspond to a “second dielectric layer” in other embodiments. A three-dimensional (3D) integra