US-12622304-B2 - Semiconductor device assembly interconnection pillars and associated methods

US12622304B2US 12622304 B2US12622304 B2US 12622304B2US-12622304-B2

Abstract

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

Inventors

Andrew M. Bayless
Cassie M. Bayless
Brandon P. Wirz

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20220728

Claims (20)

1 . A semiconductor device assembly, comprising: a first semiconductor die; a second semiconductor die; and an interconnection structure directly electrically coupling the first and the second semiconductor dies, the interconnection structure including: a first interconnection structure portion at the first semiconductor die, the first interconnection structure portion having: a first conductive pillar with a concave bonding surface, a first annular barrier layer circumferentially surrounding a sidewall of the first conductive pillar, and a first annular solder layer circumferentially surrounding the first annular barrier layer and the sidewall of the first conductive pillar, and a second interconnection structure portion at the second semiconductor die, the second interconnection structure portion having a second conductive pillar with a convex bonding surface coupled to the concave bonding surface.
2 . The semiconductor device assembly of claim 1 , wherein the second interconnection structure further includes: a second annular barrier layer surrounding a sidewall of the second conductive pillar, and a second annular solder layer surrounding the second annular barrier layer.
3 . The semiconductor device assembly of claim 1 , wherein the interconnection structure further includes an intermetallic material adjacent to the concave bonding surface and the convex bonding surface.
4 . The semiconductor device assembly of claim 3 , wherein the intermetallic material is substantially free of voiding in a central region vertically aligned with centers of the first and second conductive pillars.
5 . The semiconductor device assembly of claim 1 , wherein the first conductive pillar has a first diameter, wherein the second conductive pillar has a second diameter, and wherein the first diameter is different than the second diameter.
6 . The semiconductor device assembly of claim 1 , wherein the concave bonding surface has a first constant radius of curvature.
7 . The semiconductor device assembly of claim 1 , wherein the convex bonding surface has a second constant radius of curvature different than the first constant radius of curvature.
8 . The semiconductor device assembly of claim 1 , wherein the first conductive pillar extends a first distance from the first semiconductor die, wherein the second conductive pillar extends a second distance from the second semiconductor die, and wherein the first distance is different than the second distance.
9 . The semiconductor device assembly of claim 1 , wherein the interconnection structure is one of a plurality of substantially identical interconnection structures directly electrically coupling the first and second semiconductor dies.
10 . The semiconductor device assembly of claim 1 further comprising a third semiconductor die and a second interconnection structure, wherein the second interconnection structure directly electrically couples the first and third semiconductor dies, and wherein the second interconnection structure includes: a third interconnection structure portion identical to the first interconnection structure portion and extending from; and a fourth interconnection structure portion identical to the second interconnection structure portion.
11 . A semiconductor device, comprising: a semiconductor substrate; and an interconnection structure extending from the semiconductor substrate, the interconnection structure including: a conductive pillar having a curved bonding surface opposite the semiconductor substrate, an annular barrier layer surrounding a sidewall of the conductive pillar, and an annular solder layer surrounding the annular barrier layer and the sidewall of the conductive pillar; wherein the curved bonding surface is substantially free of solder material.
12 . The semiconductor device of claim 11 , wherein a top surface of the annular barrier layer is at an edge of the curved bonding surface.
13 . The semiconductor device of claim 11 , wherein the annular solder layer extends from the semiconductor substrate to an edge of the curved bonding surface.
14 . The semiconductor device of claim 11 , wherein a top surface of the annular solder layer is below a top surface of the annular barrier layer.
15 . The semiconductor device of claim 11 , wherein the curved bonding surface has a constant radius of curvature.
16 . The semiconductor device of claim 11 , wherein the curved bonding surface is convex.
17 . The semiconductor device of claim 11 , wherein the conductive pillar has a circular cross section.
18 . The semiconductor device of claim 11 further comprising a second interconnection structure extending from the semiconductor substrate, the second interconnection structure including: a second conductive pillar having a curved bonding surface opposite the semiconductor substrate; a second annular barrier layer surrounding a sidewall of the conductive pillar; and a second annular solder layer surrounding the annular barrier layer; wherein the curved bonding surface is substantially free of solder material.
19 . A method of manufacturing a semiconductor die interconnection structure, the method comprising: providing a first semiconductor die with a first interconnection structure portion thereon, the first interconnection structure portion including: a first conductive pillar with a concave bonding surface, a first annular barrier layer surrounding the first pillar, and a first annular solder layer surrounding the first annular barrier layer and a sidewall of the conductive pillar; providing a second semiconductor die with a second interconnection structure portion thereon, the second interconnection structure portion including a convex bonding surface; aligning the first and second semiconductor dies with the concave bonding surface interfacing and opposing the convex bonding surface; and coupling the first and second semiconductor dies together by flowing a portion of the first annular solder layer over the first annular barrier layer and between the concave and convex bonding surfaces.
20 . The method of claim 19 , wherein the second semiconductor die further comprises (i) a second conductive pillar having the convex bonding surface, (ii) a second annular barrier layer surrounding the second conductive pillar, and (iii) a second annular solder layer surrounding the second annular barrier layer, and wherein coupling further includes reflowing a portion of the second annular solder layer over the second annular barrier layer and between the concave and convex bonding surfaces.

Description

TECHNICAL FIELD The present disclosure is generally related to semiconductor device assembly interconnection structures. In particular, the present technology relates to interconnection pillars having solder on one or more lateral exterior surfaces thereof. BACKGROUND Microelectronic devices, such as memory devices and microprocessors, and other electronics typically include one or more semiconductor devices and/or components attached to one or more of a substrate, another semiconductor device, and/or component encased in a protective covering. The devices and/or components include at least one functional feature, such as memory cells, processor circuits, and/or interconnecting circuitry, etc. Each device and/or component commonly includes an array of small bond pads electrically coupled to the functional features therein for interconnection with other devices and/or components. In some applications, these bond pads interconnect with other device and/or components using metallic interconnection pillars, such as copper pillars. These pillars provide both a physical and an electrical coupling between the device and/or components they connect. Because manufacturers are under increasing pressure to reduce the space occupied by assemblies having these devices and components, while simultaneously increasing their capacity and/or speed of operation, interconnection pillars must be increasingly small while still providing sufficient physical strength and current carrying capacity. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross sectional side view of a semiconductor device assembly, configured in accordance with some embodiments of the present technology. FIG. 2 is a cross sectional side view of a semiconductor device assembly, configured in accordance with some embodiments of the present technology. FIGS. 3-9 illustrate a process for producing a semiconductor device assembly, in accordance with some embodiments of the present technology. FIG. 10 is a flow diagram illustrating a process for producing a semiconductor device assembly, in accordance with some embodiments of the present technology. FIG. 11 is a schematic diagram illustrating a semiconductor device assembly incorporating the present technology, configured in accordance with some embodiments of the present technology. The drawings have not necessarily been drawn to scale. Similarly, some components or operations can be separated into different components or combined into a single assembly in some implementations of the present technology. While the technology is amenable to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and are described in detail below. DETAILED DESCRIPTION When traditional interconnection pillars are formed, solder material is provided between opposing surfaces of interconnection pillar portions. When the solder material is heated to bond the pillar portions together, the solder material can be drawn to the edges of the surfaces, producing voids (e.g., pockets, openings, inconsistencies) near the surfaces' centers and/or throughout the solder. These voids can increase bond failure risk and/or reduce interconnection performance by, for example, decreasing bond strength and/or increasing resistance. Voids can further exacerbate these risks by pushing solder to the exterior surfaces of the pillars during assembly temperature cycling, reducing the physical and electrical integrity of the connect between pillars and devices. The devices and methods of the present technology relate to semiconductor device assemblies including interconnection structures (e.g., interconnection pillars) with outside solder for improving device interconnection integrity and reliability. A completed interconnection structure can include a first portion connected to a first device and having a first pillar with a bonding surface excluding solder material, and can also include a second portion connected to a second device and having a second pillar with a bonding surface excluding solder material. Either or both of the first and second interconnection structure portions can include solder material forming an outside surface (e.g., sidewall, side surface, exterior wall) thereof. To assemble the first and second devices together, the bonding surfaces of the first and second pillars can be aligned. Then, the solder material forming the exterior of the first and/or second interconnection structure portions can flow from the outside thereof to between the bonding surfaces, completing the interconnection structure (e.g., bonding the first and second portions together) and coupling the first and second device together. By including solder material on the outside of the first and second interconnection structure portions, and by excluding—before assembly—solder material on the bonding surfaces thereof, embodiments of the present technology can provide improvements over traditional interconnection