US-12622305-B2 - Bump with stepped passivation structure with varying step heights

US12622305B2US 12622305 B2US12622305 B2US 12622305B2US-12622305-B2

Abstract

A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.

Inventors

Hongkai JI

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230313
Priority Date: 20220930

Claims (12)

1 . A semiconductor structure, comprising: a carrying layer, a barrier layer disposed on a surface of the carrying layer, wherein the barrier layer comprises an opening inside; wherein the barrier layer comprises multiple sub-barrier layers in a stack, wherein the multiple sub-barrier layers respectively form a plurality of steps in the opening, and wherein in a direction pointing from an outside of the opening to an inside of the opening, heights of the plurality of plurality of steps decrease sequentially; a solder layer and an adhesive layer disposed inside the opening, wherein the adhesive layer covers the solder layer; wherein the carrying layer is a first substrate, and wherein the multiple sub-barrier layers comprise at least two layers; wherein the surface of the carrying layer further comprises a soldering pad, wherein the soldering pad is located in the bottommost layer of the multiple sub-barrier layers; wherein, except for the bottommost layer of the multiple sub-barrier layers, a distance between each of rest of the multiple sub-barrier layers and the soldering pad is greater than a half of a diameter of the solder layer.
2 . The semiconductor structure according to claim 1 , wherein the multiple sub-barrier layers have a same thickness; or, thicknesses of the multiple sub-barrier layers increase sequentially in a direction where the carrying layer points to the barrier layer.
3 . The semiconductor structure according to claim 1 , the plurality of steps is located on opposite sides of the opening.
4 . The semiconductor structure according to claim 3 , wherein the plurality of steps surrounds the opening.
5 . The semiconductor structure according to claim 1 , wherein the carrying layer comprises a wafer, and wherein the multiple sub-barrier layers comprise at least three layers.
6 . The semiconductor structure according to claim 5 , wherein a top surface of the solder layer is higher than a top surface of the barrier layer, or the top surface of the solder layer is flush with the top surface of the barrier layer.
7 . The semiconductor structure according to claim 6 , wherein a height difference between the top surface of the solder layer and the top surface of the barrier layer is smaller than a thickness the multiple sub-barrier layers.
8 . The semiconductor structure according to claim 1 , except for a topmost step, in the direction pointing from the outside of the opening to the inside of the opening, lengths of upper surfaces of the plurality of steps increase sequentially.
9 . The semiconductor structure according to claim 1 , wherein in the direction which the carrying layer points to the barrier layer, a thickness of the bottommost sub-barrier layer is greater than or equal to a thickness of the soldering pad.
10 . The semiconductor structure according to claim 1 , wherein a sidewall of the bottommost sub-barrier layer of the multiple sub-barrier layers is in contact with a sidewall of the soldering pad.
11 . The semiconductor structure according to claim 1 , further comprising: a structural member, wherein the structural member is located over the carrying layer and is electrically connected with the solder layer; wherein the adhesive layer fills between the structural member and the carrying layer; and wherein the structural component comprises a chip or a second substrate.
12 . A method for manufacturing a semiconductor structure, comprising: providing a carrying layer; forming a barrier layer on a surface of the carrying layer, and forming an opening in the barrier layer, wherein the barrier layer comprises multiple sub-barrier layers in a stack; forming a plurality of steps from the multiple layers of the sub-barrier layer in the opening, wherein heights of the plurality of steps are successively reduced in a direction pointing from an inside of the opening to an outside of the opening; forming a solder layer within the opening; and forming an adhesive layer covering the solder layer in the opening; wherein the carrying layer is a first substrate, and wherein the multiple sub-barrier layers comprise at least two layers; wherein the surface of the carrying layer further comprises a soldering pad, wherein the soldering pad is located in a bottommost layer of the multiple sub-barrier layers; wherein, except for the bottommost layer of the multiple sub-barrier layers, a distance between each of rest of the multiple sub-barrier layers and the soldering pad is greater than a half of a diameter of the solder layer.

Description

CROSS REFERENCES TO RELATED APPLICATIONS This application claims the benefit of priority of Chinese patent application filed on Sep. 30, 2022, entitled “A SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME”, with the application number 202211215119.1, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor structure and a method for manufacturing the semiconductor structure. BACKGROUND During the packaging process of the semiconductor structure, a solder layer is usually used to make the electrical connection between the chip and the carrier layer; however, the solder layer may deform or flow, thereby causing defects such as short circuits in the semiconductor structures. Short circuits can render semiconductor structures useless. Therefore, there is an urgent need for a semiconductor structure and a method for manufacturing the semiconductor structure to reduce the risk of defects in the semiconductor structure. SUMMARY Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, reducing the risk of defects in the semiconductor structure. According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure on the one hand, wherein the semiconductor structure includes: a carrying layer, a barrier layer is provided on the surface of the carrying layer, and an opening is provided in the barrier layer; the barrier layer includes multiple sub-barrier layers stacked, and the multiple sub-barrier layers respectively form a plurality of steps at the opening, and in the direction from the outside of the opening to the inside of the opening, a plurality of the sub-barrier layers; the height of the steps decreases successively; there is a solder layer and an adhesive layer inside the opening, and the adhesive layer covers the solder layer. According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure includes: providing a carrying layer; forming a barrier layer on the surface of the carrying layer, there is an opening in the barrier layer; the barrier layer includes multiple sub-barrier layers stacked, and the multiple sub-barrier layers form a plurality of steps at the opening, and point to the opening inside the opening In the external direction, the heights of the plurality of steps decrease sequentially; a solder layer is formed in the opening; and an adhesive layer covering the solder layer is formed in the opening. The technical scheme that the embodiment of the present disclosure provides at least has the following advantages: The surface of the carrying layer has a barrier layer, and an opening is provided in the barrier layer, and a solder layer and an adhesive layer are arranged in the opening; the multiple sub-barrier layer constitutes a step at the opening. This step can reduce the fluidity of the adhesive layer, thereby preventing the adhesive layer from rushing the solder layer out of the opening during the flow process. In addition, the steps can also guide the adhesive layer, so that the adhesive layer flows to the bottom of the opening during the filling process, thereby increasing the density of the adhesive layer and reducing the pores in the adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts. FIG. 1 shows the cross-sectional view of a semiconductor structure; FIG. 2 shows a schematic diagram of a semiconductor structure during thermocompression bonding; FIG. 3 shows an enlarged cross-sectional view of a semiconductor structure after thermocompression bonding; FIG. 4 shows a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; FIG. 5 shows the partially enlarged view of the semiconductor structure shown in FIG. 4; FIG. 6 shows the schematic diagram of the semiconductor structure shown in FIG. 5 after thermocompression bonding; FIG. 7 shows a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure; FIG. 8 shows a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure; FIGS. 9-10 respectively show top views of different steps of semiconductor structures provided by an em