US-12622306-B2 - Semiconductor device with optimized underfill flow

US12622306B2US 12622306 B2US12622306 B2US 12622306B2US-12622306-B2

Abstract

A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.

Inventors

Yihao Chen
Tim Huang
Zengyu Zhou
Rui YUan
Fen Yu
Hope Chiu

Assignees

SanDisk Technologies, Inc.

Dates

Publication Date: 20260505
Application Date: 20220321

Claims (14)

1 . A semiconductor device package comprising: a semiconductor die including: a plurality of bond pads; and an inlet side corresponding to a dispensing inlet for underfill flow; a substrate including: a first metal layer disposed at a top surface of the substrate; one or more lower metal layers disposed underneath the first metal layer; a plurality of metal contacts disposed in the first metal layer; and a plurality of trace segment lines; and a solder joint array including a plurality of solder bump rows; wherein each of the plurality of solder bump rows: is oriented substantially parallel to the inlet side of the semiconductor die; and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate; and wherein each of the plurality of trace segment lines: forms a continuous data route; is oriented substantially parallel to the inlet side of the semiconductor die; and includes: a first plurality of trace segments disposed in the first metal layer and electrically coupled to each other; and a second plurality of trace segments disposed in the one or more lower metal layers and electrically coupled to each other and to each of the first plurality of trace segments.
2 . The semiconductor device package of claim 1 , wherein the first metal layer further includes a plurality of underfill channels that are substantially perpendicular to the inlet side of the semiconductor die.
3 . The semiconductor device package of claim 2 , wherein the plurality of underfill channels include regions corresponding to the second plurality of trace segments.
4 . The semiconductor device package of claim 1 , wherein, for each of the plurality of trace segment lines, each trace segment of the second plurality of trace segments has a length of at least a distance between two adjacent solder bumps.
5 . The semiconductor device package of claim 1 , wherein, for each of the plurality of trace segment lines, regions of the first metal layer between trace segments of the first plurality of trace segments are free from metal.
6 . The semiconductor device package of claim 1 , wherein, for each of the plurality of trace segment lines, regions of the first metal layer corresponding to trace segments of the second plurality of trace segments are free from metal.
7 . The semiconductor device package of claim 1 , wherein: the plurality of trace segment lines includes a first trace segment line and a second trace segment line adjacent to the first trace segment line; and segments of the first trace segment line that are free from metal in the first metal layer substantially overlap with segments of the second trace segment line that are free from metal in the first metal layer.
8 . The semiconductor device package of claim 7 , wherein the substantially overlapping segments that are free from metal form an underfill flow channel in the first metal layer.
9 . The semiconductor device package of claim 1 , wherein: the semiconductor die is rectangular, including two sides having a first length and two sides having a second length shorter than the first length; and the inlet side is one of the two sides having the first length.
10 . The semiconductor device package of claim 1 , wherein, for each of the plurality of trace segment lines, trace segments in the first plurality of trace segments are electrically connected to trace segments in the second plurality of trace segments with vias disposed between the first metal layer and the one or more lower metal layers.
11 . A semiconductor device package comprising: a semiconductor die including: a plurality of bond pads; and an inlet side corresponding to a dispensing inlet for underfill flow; substrate means including: a first metal layer disposed at a top surface of the substrate; one or more lower metal layers disposed underneath the first metal layer; a plurality of metal contacts disposed in the first metal layer; and a plurality of trace segment lines; and solder joint means including a plurality of solder bump rows; wherein each of the plurality of solder bump rows: is oriented substantially parallel to the inlet side of the semiconductor die; and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate; and wherein each of the plurality of trace segment lines: forms a continuous data route; is oriented substantially parallel to the inlet side of the semiconductor die; and includes: a first plurality of trace segments disposed in the first metal layer and electrically coupled to each other; and a second plurality of trace segments disposed in the one or more lower metal layers and electrically coupled to each other and to each of the first plurality of trace segments.
12 . The semiconductor device package of claim 11 , wherein the first metal layer further includes a plurality of underfill channels that are substantially perpendicular to the inlet side of the semiconductor die.
13 . The semiconductor device package of claim 12 , wherein the plurality of underfill channels include regions corresponding to the second plurality of trace segments.
14 . The semiconductor device package of claim 12 , wherein, for each of the plurality of trace segment lines, each trace segment of the second plurality of trace segments has a length of at least a distance between two adjacent solder bumps.

Description

BACKGROUND A semiconductor device package may include one or more semiconductor dies packaged together on a substrate. A die may be coupled to the substrate using flip chip mounting, in which connections between the die and the substrate are formed using an array of solder joints. The solder joints may be positioned over and coupled to corresponding metal contacts and traces in the substrate. An underfill material may reduce thermal stresses on the solder joints and corresponding metal contacts. As semiconductor memory packages continue to increase in storage capacity and complexity, the solder joint array increases in complexity, which causes the layout of the metal traces in the substrate to increase in complexity. The metal traces may become thicker, longer, and/or more numerous in order to accommodate the increased quantity of solder joints in the array. The layout of the resulting traces may obstruct the flow of underfill during the manufacturing process, leaving voids in areas that are expected to be covered in underfill, which may have the undesired effect of weakening the solder joints in these areas. SUMMARY The present disclosure describes a semiconductor device package having an improved trace layout in the top layer of the substrate, thereby improving underfill flow during the manufacturing process. In one improved trace layout, gaps are introduced in longer traces oriented perpendicular to the direction of underfill flow by using vias to periodically route the traces through a lower layer in the substrate. In another improved trace layout, longer traces are reoriented to be parallel to the direction of underfill flow. Thus, the improved trace layouts described herein decrease obstructions to the flow of underfill during the manufacturing process, thereby decreasing the occurrence of underfill voids, which has the desired effect of consistently strong solder joint arrays in the semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing summary, as well as the following detailed description, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, there are shown in the drawings embodiments which are presently preferred, wherein like reference numerals indicate like elements throughout. It should be noted, however, that aspects of the present disclosure can be embodied in different forms and thus should not be construed as being limited to the illustrated embodiments set forth herein. The elements illustrated in the accompanying drawings are not necessarily drawn to scale, but rather, may have been exaggerated to highlight the important features of the subject matter therein. Furthermore, the drawings may have been simplified by omitting elements that are not necessarily needed for the understanding of the disclosed embodiments. FIG. 1 is a cross-sectional side view of a semiconductor device package including a semiconductor die coupled to a substrate using flip chip mounting. FIG. 2 is a detailed view of a portion of the semiconductor device package depicted in FIG. 1. FIG. 3 is a perspective view of a solder joint array and corresponding bond pads in a semiconductor device package. FIGS. 4A-4B are views of a solder joint array and corresponding trace layout including long traces that are perpendicular to the direction of underfill flow. FIGS. 5A-5B are views of a solder joint array and corresponding trace layout including long traces that are perpendicular to the direction of underfill flow and include gaps for underfill flow in accordance with some implementations. FIGS. 6A-6B are views of a solder joint array and corresponding trace layout including long traces that are parallel to the direction of underfill flow in accordance with some implementations. DETAILED DESCRIPTION The present subject matter will now be described more fully hereinafter with reference to the accompanying Figures, in which representative embodiments are shown. The present subject matter can, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. For example, although a semiconductor device for an SSD is discussed, it will be apparent to those of skill in the art that the concepts disclosed herein have much broader application than just SSDs. Thus, these embodiments are provided to describe and enable one of skill in the art. The elements illustrated in the accompanying FIGURES are not necessarily drawn to scale, but rather, may have been exaggerated to highlight the important features of the subject matter therein. Furthermore, the Figures may have been simplified by omitting elements that are not necessarily needed for the understanding of the disclosed embodiments. FIG. 1 is a diagram illustrating an example semiconductor device 100 (also referred to as a semiconductor package, semiconductor device package, or semiconductor memory package). Device 100 may be any type of se