US-12622307-B2 - Controlled grain growth for bonding and bonded structure with controlled grain growth

Abstract

Disclosed is an element including a conductive feature at a contact surface of the element and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded. The contact feature includes a conductive material and an amount of impurities at a grain boundary of the conductive material. The impurities have a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.

Inventors

• Jeremy Alfred Theil
• Cyprian Emeka Uzoh
• Guilian Gao

Assignees

• ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Dates

Publication Date

20260505

Application Date

20221221

Claims (20)

1. 1 . An element comprising: a conductive feature at a contact surface of the element including a conductive material and an amount of impurities at a grain boundary of the conductive material, the impurities having a material that does not form an alloy with the conductive material at 400° C.; and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded, wherein the impurities are co-deposited with the conductive material such that a first concentration of the impurities near the contact surface of the conductive feature is similar to a second concentration of the impurities in an interior of the conductive feature.
2. 2 . The element of claim 1 , wherein the impurities comprise a non-metallic compound.
3. 3 . The element of claim 1 , wherein the conductive material comprises copper.
4. 4 . The element of claim 3 , wherein the impurities comprise a refractory material.
5. 5 . The element of claim 3 , wherein the impurities comprise tantalum.
6. 6 . The element of claim 3 , wherein the impurities comprise zirconium.
7. 7 . The element of claim 3 , wherein the impurities comprise molybdenum.
8. 8 . The element of claim 1 , wherein the conductive feature is configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature, and wherein a bonding temperature is in a range of 100° C. to 250° C.
9. 9 . The element of claim 1 , wherein the impurities are disposed to cover 5% to 75% of grain boundaries of the conductive material.
10. 10 . The element of claim 1 , wherein the conductive feature comprises 20 parts per million (ppm) to 5000 ppm of the impurities.
11. 11 . A bonded structure comprising: a first element including a first conductive feature and a first nonconductive region at a first contact surface of the first element; and a second element including a second conductive feature directly bonded to the first conductive feature to define bonded conductive features, and a second nonconductive region directly bonded to the first nonconductive region, wherein the bonded conductive features include a conductive material and a concentration of impurities, the impurities comprising nanoparticles that do not form an alloy with the conductive material at 400° C.
12. 12 . The bonded structure of claim 11 , wherein the nanoparticles comprise a non-metallic compound.
13. 13 . The bonded structure of claim 11 , wherein the conductive material comprises copper.
14. 14 . The bonded structure of claim 13 , wherein the nanoparticles comprise a refractory material.
15. 15 . The bonded structure of claim 13 , wherein the nanoparticles comprise tantalum.
16. 16 . The bonded structure of claim 13 , wherein the nanoparticles comprise zirconium.
17. 17 . The bonded structure of claim 13 , wherein the nanoparticles comprise molybdenum.
18. 18 . The bonded structure of claim 11 , wherein the conductive feature is configured such that grains of the conductive material grow slower than the conductive material without the nanoparticles at room temperature.
19. 19 . The element of claim 1 , wherein the impurities do not form an alloy with the conductive material between 100° C. and 400° C.
20. 20 . The element of claim 1 , wherein the impurities do not form an alloy with the conductive material at 250° C.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63/293,300, filed Dec. 23, 2021, titled “CONTROLLED GRAIN GROWTH FOR BONDING AND BONDED STRUCTURE WITH CONTROLLED GRAIN GROWTH,” the entire contents of which are hereby incorporated by reference herein in their entirety and for all purposes. BACKGROUND Field The field relates to a conductive feature with controlled grain growth. Description of the Related Art Semiconductor elements, such as integrated device dies or chips, may be mounted or stacked on other elements. For example, a semiconductor element can be mounted to a carrier, such as a package substrate, an interposer, a reconstituted wafer or element, etc. As another example, a semiconductor element can be stacked on top of another semiconductor element, e.g., a first integrated device die can be stacked on a second integrated device die. Each of the semiconductor elements can have conductive pads for mechanically and electrically bonding the semiconductor elements to one another. There is a continuing need for improved methods for forming the conductive pads for reliable bonding. BRIEF DESCRIPTION OF THE DRAWINGS The detailed description is set forth with reference to the accompanying figures. The use of the same reference numbers in different figures indicates similar or identical items. For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternatively, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure. These aspects and others will be apparent from the following description of preferred embodiments and the accompanying drawings, which are meant to illustrate and not to limit the invention, wherein: FIG. 1A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature with relatively low or minimum impurity concentrations, shown after plating, with impurities schematically illustrated, according to one embodiment. FIG. 1B is a representation of the grain structure shown in FIG. 1A, but shown just before annealing, according to one embodiment. FIG. 1C is a representation of the grain structure shown in FIG. 1A, but shown after annealing, according to one embodiment. FIG. 2A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature having impurity concentrations selected to manage grain growth, shown after plating, with impurities schematically illustrated, according to one embodiment. FIG. 2B is a representation of the grain structure shown in FIG. 2A, but shown just before annealing, according to one embodiment. FIG. 2C is a representation of the grain structure shown in FIG. 2A, but shown after annealing, according to one embodiment. FIG. 3A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature with relatively high impurity concentrations, shown after plating, with impurities schematically illustrated, according to one embodiment. FIG. 3B is a representation of the grain structure shown in FIG. 3A, but shown just before annealing, according to one embodiment. FIG. 3C is a representation of the grain structure shown in FIG. 3A, but shown after annealing, according to one embodiment. FIGS. 4A-4D present a series of schematic side sectional views that show a multi-step method by which an element can be formed, according to one embodiment. FIG. 4E is a schematic side sectional view of a first and second element prepared to be directly bonded, according to one embodiment. FIG. 4F is a schematic side sectional view of the first and second elements from FIG. 4E after being directly bonded, according to one embodiment. DETAILED DESCRIPTION The present disclosure describes methods of controlling metallic grain growth of conductive features (e.g., conductive pads, through-substrate vias (TSVs), etc.) in elements, such as microelectronic elements. Various embodiments disclosed herein can be advantageous for direct metal bonding, such as direct hybrid bonding. For example, as schematically demonstrated in FIGS. 4E and 4F, two or more semiconductor elements 102, 152 (such as integrated device dies, wafers, etc.) may be stacked on or bonded to one another to form a bonded structure 100. Conductive features 206 of one element 102 may be electrically connected to corresponding conductive features 156 of another element (e.g., a second element 152). Any suitable number of elements can be stacked in the bonded structure 100. The methods and conductive feature structures described herein can be useful in other contexts as well. In some embodiments, the eleme