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US-12622308-B2 - Interconnect structure for advanced packaging and method for the same

US12622308B2US 12622308 B2US12622308 B2US 12622308B2US-12622308-B2

Abstract

An interconnect structure for advanced packaging and method for the interconnect structure are disclosed. The method includes: providing a semiconductor substrate to be packaged having surface on which there is a first pad having conduction-promoting surface; depositing a first passivation layer on surface of the semiconductor substrate, the first pad is exposed from first passivation layer, forming a wiring layer on surface of the first passivation layer by screen printing, and forming a metal layer on surface of the wiring layer by electroless plating, wherein the wiring layer covers the first pad; forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein there is a through hole in the second passivation layer, in which the metal layer is exposed; and forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole.

Inventors

  • Yonggang Jin

Assignees

  • OIP TECHNOLOGY PTE LTD.

Dates

Publication Date
20260505
Application Date
20230413
Priority Date
20230307

Claims (11)

  1. 1 . A method for an interconnect structure for advanced packaging, comprising the steps of: step S 1 : providing a semiconductor substrate to be packaged having a surface on which there is a first pad, the first pad connected to an internal circuit of the semiconductor substrate to be packaged, the first pad having a conduction-promoting surface; step S 2 : depositing a first passivation layer on the surface of the semiconductor substrate to be packaged, wherein the first pad is exposed from the first passivation layer, forming a wiring layer on a surface of the first passivation layer by screen printing, and forming a metal layer on a surface of the wiring layer by electroless plating, thereby forming an interconnect, wherein the wiring layer covers the first pad; step S 3 : forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein the second passivation layer has a through hole formed therein, the metal layer is exposed in the through hole; and step S 4 : forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole, wherein the step S 1 comprises: providing the semiconductor substrate to be packaged having the surface on which there is the first pad connected to the internal circuit of the semiconductor substrate to be packaged, wherein the first pad is an aluminum pad; and forming a gold bump on a surface of the first pad by punching a gold wire thereon using a bonding machine, thereby turning the surface of the first pad into the conduction-promoting surface.
  2. 2 . The method of claim 1 , wherein the gold bump has a thickness of 2 μm to 7 μm.
  3. 3 . The method of claim 1 , wherein the step S 1 comprises: providing the semiconductor substrate to be packaged having the surface on which there is the first pad connected to the internal circuit of the semiconductor substrate to be packaged, wherein the first pad is an aluminum pad; and forming a nickel-gold layer on a surface of the first pad by electroless plating, thereby turning the surface of the first pad into the conduction-promoting surface.
  4. 4 . The method of claim 3 , wherein the nickel-gold layer has a thickness of 1 μm to 5 μm.
  5. 5 . The method of claim 1 , wherein the step S 2 comprises: depositing the first passivation layer on the surface of the semiconductor substrate to be packaged, wherein the first pad is exposed from the first passivation layer; forming the wiring layer by screen printing and curing a metal paste on the first passivation layer; and forming the metal layer on the wiring layer by electroless plating, thereby forming the interconnect.
  6. 6 . The method of claim 5 , wherein the metal paste includes silver paste, tungsten paste and gold paste.
  7. 7 . The method of claim 5 , wherein the formation of the metal layer comprises: forming the metal layer by electroless plating of copper, nickel-gold or nickel-palladium-gold on the wiring layer, thereby forming the interconnect.
  8. 8 . The method of claim 1 , wherein the step S 4 comprises: forming the second pad by electroless plating of nickel-gold in the through hole, which fills the through hole and covers the second passivation layer around the opening of the through hole.
  9. 9 . The method of claim 1 , further comprising, subsequent to the step S 4 , forming a solder ball on the second pad by BGA packaging.
  10. 10 . An interconnect structure for advanced packaging, fabricated using the method of claim 1 , the interconnect structure comprising: a semiconductor substrate to be packaged having a surface on which there is a first pad, the first pad connected to an internal circuit of the semiconductor substrate to be packaged, the first pad having a conduction-promoting surface; a first passivation layer covering the surface of the semiconductor substrate to be packaged, the first pad is exposed from the first passivation layer; an interconnect comprising a wiring layer and a metal layer, the wiring layer residing on part of a surface of the first passivation layer and covering the first pad, the metal layer residing on the wiring layer; a second passivation layer covering the first passivation layer and the interconnect, wherein the second passivation layer has a through hole formed therein, the metal layer is exposed in the through hole; and a second pad filling the through hole and covering the second passivation layer around an opening of the through hole, wherein the first pad is an aluminum pad and formed on a surface thereof with a gold bump or a nickel-gold layer, and the gold bump has a thickness of 2 μm to 7 μm.
  11. 11 . The interconnect structure of claim 10 , wherein the nickel-gold layer has a thickness of 1 μm to 5 μm.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application claims the priority of Chinese patent application number 202310233450.4, filed on Mar. 7, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present invention relates to the field of semiconductor technology and, in particular, to an interconnect structure for advanced packaging and a method for the interconnect structure. BACKGROUND The ever-increasing circuit density and continuous miniaturization of next-generation semiconductor devices have brought about the need for advanced packaging of such semiconductor devices. The so-called advanced packaging is wafer-level packaging and currently often involves physical vapor deposition (PVD), photolithography and etching processes for the fabrication of interconnect structures. These processes are expensive and time-consuming and require hermeticity of the involved equipment. SUMMARY OF THE INVENTION It is an objective of the present invention to provide an interconnect structure for advanced packaging and a method for the interconnect structure, which can reduce the process cost and time required for the fabrication of interconnect structures. To this end, the present invention provides a method for an interconnect structure for advanced packaging, including the steps of: step S1: providing a semiconductor substrate to be packaged having a surface on which there is a first pad connected to an internal circuit of the semiconductor substrate to be packaged, the first pad having a conduction-promoting surface;step S2: depositing a first passivation layer on the surface of the semiconductor substrate to be packaged, the first pad is exposed from the first passivation layer, forming a wiring layer on a surface of the first passivation layer by screen printing, and forming a metal layer on a surface of the wiring layer by electroless plating, thereby forming an interconnect, wherein the wiring layer covers the first pad;step S3: forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein there is a through hole in the second passivation layer, in which the metal layer is exposed; andstep S4: forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole. Optionally, step S1 may include: providing the semiconductor substrate to be packaged having the surface on which there is the first pad connected to the internal circuit of the semiconductor substrate to be packaged, wherein the first pad is an aluminum pad; andforming a gold bump on a surface of the first pad by punching a gold wire thereon using a bonding machine, thereby turning the surface of the first pad into the conduction-promoting surface. Additionally, the gold bump may have a thickness of 2 μm to 7 μm. Optionally, step S1 may include: providing the semiconductor substrate to be packaged having the surface on which there is the first pad connected to the internal circuit of the semiconductor substrate to be packaged, wherein the first pad is an aluminum pad; andforming a nickel-gold layer on a surface of the first pad by electroless plating, thereby turning the surface of the first pad into the conduction-promoting surface. Additionally, the nickel-gold layer may have a thickness of 1 μm to 5 μm. Optionally, step S2 may include: depositing the first passivation layer on the surface of the semiconductor substrate to be packaged, the first pad is exposed from the first passivation layer;forming the wiring layer by screen printing and curing a metal paste on the first passivation layer; andforming the metal layer on the wiring layer by electroless plating, thereby resulting in the formation of the interconnect. Additionally, the metal paste may include silver paste, tungsten paste and gold paste. Additionally, the formation of the metal layer may include: forming the metal layer by electroless plating of copper, nickel-gold or nickel-palladium-gold on the wiring layer, thereby resulting in the formation of the interconnect. Optionally, step S4 may include: forming the second pad by electroless plating of nickel-gold in the through hole, which fills the through hole and covers the second passivation layer around the opening of the through hole. Optionally, the method may further include, subsequent to step S4, forming a solder ball on the second pad by BGA packaging. In another aspect, the present invention provides an interconnect structure for advanced packaging, fabricated using the method as defined above. The interconnect structure includes: a semiconductor substrate to be packaged having a surface on which there is a first pad connected to an internal circuit of the semiconductor substrate to be packaged, the first pad having a conduction-promoting surface;a first passivation layer covering the surface of the semiconductor substrate to be packaged, the first pad is exposed