US-12622310-B2 - Wafer level fan out semiconductor device and manufacturing method thereof

Abstract

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Inventors

• Boo Yang Jung
• Jong Sik Paek
• Choon Heung Lee
• In Bae Park
• Sang Won Kim
• Sung Kyu Kim
• Sang Gyu Lee

Assignees

• Amkor Technology Singapore Holding Pte. Ltd.

Dates

Publication Date

20260505

Application Date

20231221

Claims (20)

1. 1 . A semiconductor device, comprising: a semiconductor die comprising a semiconductor die top side, a semiconductor die bottom side, and a semiconductor die lateral side between the semiconductor die top side and the semiconductor die bottom side; a bond pad coupled to the semiconductor die top side; a passivation layer comprising a passivation layer top side, a passivation layer bottom side, and a passivation layer lateral side between the passivation layer top side and the passivation layer bottom side, wherein the passivation layer bottom side contacts the semiconductor die top side, and wherein the passivation layer top side comprises an opening that exposes the bond pad; a first sealing part comprising a first sealing part top side and a first sealing part bottom side, wherein the first selecting part is coupled to the semiconductor die lateral side and in direct contact with the passivation layer lateral side; a dielectric structure comprising a dielectric structure top side and a dielectric structure bottom side, wherein the dielectric structure bottom side is on and in contact with the first sealing part top side; a conductive land positioned over the dielectric structure and peripherally beyond the semiconductor die lateral side; a conductive path comprising a conductive path first end coupled to the bond pad and a conductive path second end coupled to the conductive land, wherein at least a portion of the dielectric structure is located vertically between the conductive path and the first sealing part top side; a conductive interconnection structure coupled to the conductive land such that the conductive interconnection structure is positioned peripherally beyond the semiconductor die lateral side; and a second sealing part comprising a second sealing part top side and a second sealing part bottom side, wherein the second sealing part contacts and encapsulates at least 10% of a total height of the conductive interconnection structure.
2. 2 . The semiconductor device of claim 1 , wherein the second sealing part comprises a single encapsulant layer.
3. 3 . The semiconductor device of claim 1 , wherein the second sealing part does not encapsulate more than 50% of the total height of the conductive interconnection structure.
4. 4 . The semiconductor device of claim 1 , wherein a thermal expansion coefficient of the first sealing part is equal to a thermal expansion coefficient of the second sealing part.
5. 5 . The semiconductor device of claim 1 , wherein: the conductive path comprises a conductive trace extending laterally along the dielectric structure; and the second sealing part bottom side contacts the dielectric structure top side and a top side of the conductive trace.
6. 6 . The semiconductor device of claim 1 , wherein the first sealing part bottom side is coplanar with the semiconductor die bottom side.
7. 7 . The semiconductor device of claim 6 , wherein the semiconductor die bottom side provides an external side of the semiconductor device.
8. 8 . The semiconductor device of claim 1 , wherein the first sealing part covers the semiconductor die bottom side.
9. 9 . The semiconductor device of claim 1 , wherein: a dielectric constant of the dielectric structure is lower than a dielectric constant of the first sealing part; and the dielectric constant of the dielectric structure is lower than a dielectric constant of the second sealing part.
10. 10 . The semiconductor device of claim 1 , wherein: the dielectric structure is softer than the first sealing part; and the dielectric structure is softer than the second sealing part.
11. 11 . A semiconductor device, comprising: a semiconductor die comprising a semiconductor top side, a semiconductor die bottom side, a semiconductor die lateral side between the semiconductor die top side and the semiconductor die bottom side; a bond pad coupled to the semiconductor top side; a passivation layer contacting the semiconductor die top side, wherein the passivation layer comprises a passivation layer top side, a passivation layer bottom side, a passivation layer lateral side between the passivation layer top side and the passivation layer bottom side, and an opening in the passivation layer top side that exposes the bond pad; a first sealing part comprising a first sealing part top side and a first sealing part bottom side, wherein the first sealing part is coupled to the semiconductor die lateral side and in direct contact with the passivation layer lateral side; a dielectric structure comprising a dielectric structure top side and a dielectric structure bottom side, wherein the dielectric structure bottom side is on and in contact with the first sealing part; a conductive path comprising a conductive path first end and a conductive path second end, wherein the conductive path first end is coupled to the bond pad and the conductive path second end is positioned peripherally beyond the semiconductor die lateral side, and wherein at least a portion of the dielectric structure is located vertically between the conductive path and the first sealing part top side; a conductive interconnection structure coupled to the conductive path second end such that the conductive interconnection structure is positioned peripherally beyond the semiconductor die lateral sides; and a second sealing part over the first sealing part top side and the conductive path, wherein the second sealing part surrounds at least 10% of a total height of the conductive interconnection structure.
12. 12 . The semiconductor device of claim 11 , wherein the second sealing part comprises a single encapsulant layer.
13. 13 . The semiconductor device of claim 11 , wherein the second sealing part does not encapsulate more than 50% of the total height of the conductive interconnection structure.
14. 14 . The semiconductor device of claim 11 , wherein a thermal expansion coefficient of the first sealing part is equal to a thermal expansion coefficient of the second sealing part.
15. 15 . The semiconductor device of claim 11 , wherein: the conductive path comprises a conductive trace extending laterally along the dielectric structure; and the second sealing part bottom side contacts the dielectric structure top side and a top side of the conductive trace.
16. 16 . The semiconductor device of claim 11 , wherein the first sealing part bottom side is coplanar with the semiconductor die bottom side.
17. 17 . The semiconductor device of claim 16 , wherein the semiconductor die bottom side provides an external side of the semiconductor device.
18. 18 . The semiconductor device of claim 11 , wherein the first sealing part covers the semiconductor die bottom side.
19. 19 . A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor die comprising a semiconductor die top side, a semiconductor die bottom side, and a semiconductor die lateral side between the semiconductor die top side and the semiconductor die bottom side; providing a bond pad coupled to the semiconductor die top side; providing a passivation layer comprising a passivation layer top side, a passivation layer bottom side, and a passivation layer lateral side between the passivation layer top side and the passivation layer bottom side, wherein the passivation layer bottom side contacts the semiconductor die top side, and wherein the passivation layer top side comprises an opening that exposes the bond pad; providing a first sealing part comprising a first sealing part top side and a first sealing part bottom side, wherein the first selecting part is coupled to the semiconductor die lateral side and in direct contact with the passivation layer lateral side; providing a dielectric structure comprising a dielectric structure top side and a dielectric structure bottom side, wherein the dielectric structure bottom side is on and in contact with the first sealing part top side; providing a conductive land positioned over the dielectric structure and peripherally beyond the semiconductor die lateral side; providing a conductive path comprising a conductive path first end coupled to the bond pad and a conductive path second end coupled to the conductive land, wherein at least a portion of the dielectric structure is located vertically between the conductive path and the first sealing part top side; providing a conductive interconnection structure coupled to the conductive land such that the conductive interconnection structure is positioned peripherally beyond the semiconductor die lateral side; and providing a second sealing part comprising a second sealing part top side and a second sealing part bottom side, wherein the second sealing part contacts and encapsulates at least 10% of a total height of the conductive interconnection structure.
20. 20 . The method of claim 19 , wherein: the conductive path comprises a conductive trace extending laterally along the dielectric structure; and the second sealing part bottom side contacts the dielectric structure top side and a top side of the conductive trace.

Description

TECHNICAL FIELD The present application relates to a wafer level fan out semiconductor device and a manufacturing method thereof. BACKGROUND To cope with the trend towards smaller, lighter and higher-functionality electronic products, demand for smaller, lighter and higher-functionality electronic components integrated therein is being driven. Such demand has brought advances in various semiconductor packaging techniques along with semiconductor designing and manufacturing techniques, representative examples thereof may include an area array type, a ball grid array (BGA) type based on a surface mount type packaging technique, a flip-chip type, a chip size package (CSP) type, a wafer level fan out semiconductor device, and so on. In the conventional wafer level fan out semiconductor device, a warpage phenomenon may undesirably occur to the completed device. Further, in the conventional wafer level fan out semiconductor device, solder balls may be easily detached during thermal expansion or shrinkage. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a wafer level fan out semiconductor device according to an embodiment; FIG. 2 is a cross-sectional view of a wafer level fan out semiconductor device according to another embodiment; FIG. 3 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment; FIG. 4 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment; FIG. 5 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment; FIG. 6 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment; FIG. 7 is a flowchart illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment; FIGS. 8A, 8B, 8C, and 8D are cross-sectional views sequentially illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment; FIG. 9 is a flowchart illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment; and FIGS. 10A, 10B, 10C, 10D, and 10E are cross-sectional views sequentially illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment. Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. DETAILED DESCRIPTION As an overview and in accordance with one embodiment, referring to FIG. 1, a wafer level fan out semiconductor device 100 includes a semiconductor die 110 having a first surface 111, a second surface 112, third surfaces 113 between the first surface 111 and the second surface 112, bond pads 114 coupled to the first surface 111, and a passivation layer 115 coupled the first surface 111 and having openings therein exposing the bond pads 114. A first sealing part 120 is coupled to the third surfaces 113 of the semiconductor die 110. Redistribution layers 130 have first ends coupled to the bond pads 114 and extend on to at least the passivation layer 115. Solder balls 140 are coupled to ball lands 131 of the redistribution layers 130. Further, a second sealing part 150 encapsulates the passivation layer 115, the first sealing part 120, the redistribution layers 130, and lower portions of the solder balls 140. In one embodiment, the first sealing part 120 and the second sealing part 150 have the same thermal expansion coefficient thus minimizing warpage of the wafer level fan out semiconductor device 100. Further, since the solder balls 140 are fixed and locked by the second sealing part 150 to the ball lands 131 of the redistribution layers 130, detachment between the redistribution layers 130 and the solder balls 140 is suppressed. In addition, since the second surface 112 of the semiconductor die 110 is exposed to the outside, heat dissipation efficiency of the semiconductor die 110 is maximized. Now in more detail, referring to FIG. 1, a cross-sectional view of a wafer level fan out semiconductor device 100 is illustrated. As illustrated in FIG. 1, the wafer level fan out semiconductor device 100 includes a semiconductor die 110, a first sealing part 120, a plurality of redistribution layers 130, a plurality of solder balls 140, and a second sealing part 150. The semiconductor die 110 includes a first surface 111 that is approximately planar, a second surface 112 that is approximately planar and opposite to the first surface 111, and a plurality of third surfaces 113 that are disposed between the first surface 111 and the second surface 112 and are substantially planar. In addition, the semiconductor die 110 may further include a plurality of bond pads 114 formed on the first surface 111. First surface 111, second surface 112 and third surfaces 113 are sometimes called an active surface 111, an ina