US-12622311-B2 - Method for assembling EIC to PIC to build an optical engine

US12622311B2US 12622311 B2US12622311 B2US 12622311B2US-12622311-B2

Abstract

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop/interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop/interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.

Inventors

Sukeshwar Kannan
Near Margalit
Vivek Raghuraman
Vivek Raghunathan

Assignees

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Dates

Publication Date: 20260505
Application Date: 20230814

Claims (7)

1 . An integrated circuit comprising: a first substrate comprising a first side and a second side; a circuit disposed on the first side; a first dielectric layer positioned on the circuit, the first dielectric layer comprising a first surface; a second dielectric layer positioned on the second side, the second dielectric layer comprising a second surface; a first metal layer embedded in the first dielectric layer, the first metal layer being coupled to the circuit; a second metal layer positioned on the first surface, the second metal layer being coupled to the first metal layer; a first contact coupled to the second metal layer; a via comprising a first end and a second end, the first end being coupled to the first metal layer and a second end being positioned on the second surface and coupled to the second dielectric layer; a second substrate comprising a third, a fourth side, and a trench, the trench comprising a sidewall and a bottom; a third dielectric layer positioned on the third side, the third dielectric layer comprising a third surface; a third metal layer positioned on the third dielectric layer; a second contact coupled to the third metal layer and positioned on the third surface, the second contact being coupled to the second end of the via, the second surface being contacted with the third surface; a fourth metal layer positioned on the fourth side and on the sidewall to couple to the third metal layer at the bottom; and a third contact coupled to the fourth metal layer.
2 . The integrated circuit of claim 1 , wherein the first contact comprises a metal bump configured to couple to an electrical contact on a printed circuit board.
3 . The integrated circuit of claim 1 , wherein the first substrate comprises a silicon wafer with a first thickness in a range of 10 to 12 um.
4 . The integrated circuit of claim 1 , wherein the second substrate comprises a silicon wafer with a second thickness of 75 um or greater.
5 . The integrated circuit of claim 1 , wherein the second contact comprises a metal pad.
6 . The integrated circuit of claim 5 , comprising a two-substrate stack formed by dielectric bonding between the second dielectric layer and the third dielectric layer and metal bonding between the metal pad and the second end of the via.
7 . The integrated circuit of claim 1 , wherein the third contact comprises a metal pillar with a solder cap configured to couple to an electrical contact of a photonic integrated circuit on a third substrate.

Description

FIELD OF INVENTION The subject technology is directed to silicon photonics devices and methods of manufacturing. BACKGROUND OF THE INVENTION The progress of high-speed data communication involved in SERDES devices demands further for shorter die to die interconnect path such as using vertical integration techniques to assemble different integrated circuits. For example, optical engines for the high-speed data communication can be built by silicon photonics technology that requires the stacking of electronic integrated circuit (EIC) and photonic integrated circuit (PIC). 3D stacking of silicon photonics offers a range of advantages including enhanced device density, improved performance, and shorter interconnect lengths which can lead to lower power consumption and delay. As technology node continues to push to 7 nm or smaller, some existing assembly flows may experience various technical challenges or limitations. Therefore, improved methods for assembling EIC to PIC are desired and subjects of this application. BRIEF DESCRIPTION OF THE DRAWINGS A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. FIG. 1 is a snapshot diagram of a front-end-of-life (FEOL) process step of a method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 2 is a snapshot diagram of a middle-of-life (MOL) and back-end-of-line (BEOL) process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 3 is a snapshot diagram of a through-silicon via (TSV) integration process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 4 is a snapshot diagram of a BEOL and frontside contact formation process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 5 is a snapshot diagram of a frontside carrier bond and flip wafer process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 6 is a snapshot diagram of a backside dry polish process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 7 is a snapshot diagram of a backside Si recess etching process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 8 is a snapshot diagram of a backside passivation process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 9 is a snapshot diagram of a backside chemical-mechanical polish (CMP) process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 10 is a snapshot diagram of a step of providing a short-loop/interposer wafer of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 11 is a snapshot diagram of hybrid bonding of the short-loop/interposer wafer and debonding of the carrier wafer process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 12 is a snapshot diagram of a trench-forming process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 13 is a snapshot diagram of a backside redistribution layer process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. FIG. 14 is a snapshot diagram of a backside contact formation process step of the method for preparing electronic integrated circuit to build an optical engine according to an embodiment of the subject technology. DETAILED DESCRIPTION OF THE INVENTION The current invention relates to semiconductor devices and manufacturing methods. Specifically, it presents a method for preparing an electronic integrated circuit for the assembly of an optical engine. The method involves the hybrid front-to-back bonding of a short-loop (SL) wafer t