US-12622312-B2 - Multichip module supports and related methods

Abstract

Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

Inventors

• Francis J. Carney
• Michael J. Seddon

Assignees

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Dates

Publication Date

20260505

Application Date

20220801

Claims (20)

1. 1 . A method of forming a semiconductor device package comprising: permanently coupling a material to a first semiconductor die and to a second semiconductor die at a largest planar surface, a thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die; and reducing a warpage of the largest planar surface of the first semiconductor die and a warpage of the largest planar surface of the second semiconductor die comprised in the semiconductor device package to less than 200 microns through the material; wherein the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die lie in a same plane.
2. 2 . The method of claim 1 , wherein the material comprises two or more layers.
3. 3 . The method of claim 1 , wherein the thickness is between 0.1 microns and 125 microns.
4. 4 . The method of claim 1 , wherein permanently coupling the material to the first semiconductor die and to the second semiconductor die occurs after the first semiconductor die and the second semiconductor die have been singulated from a substrate comprising a plurality of semiconductor die.
5. 5 . The method of claim 1 , wherein the material comprises a mold compound.
6. 6 . The method of claim 1 , wherein a perimeter of the first semiconductor die comprises a closed shape and a perimeter of the second semiconductor die comprises a closed shape.
7. 7 . The method of claim 1 , further comprising permanently coupling a second material to the first semiconductor die and to the second semiconductor die at the largest planar surface, the thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die.
8. 8 . The method of claim 7 , wherein the material and the second material comprise permanent die support structures.
9. 9 . A method of forming a semiconductor device package comprising: temporarily coupling a material to a first semiconductor die and to a second semiconductor die at a largest planar surface, a thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die; reducing a warpage of the largest planar surface of the first semiconductor die and a warpage of the largest planar surface of the second semiconductor die comprised in the semiconductor device package to less than 200 microns through the material; and removing the material from the first semiconductor die and the second semiconductor die; wherein the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die lie in a same plane.
10. 10 . The method of claim 9 , further comprising removing the material using one of light, etching, peeling, ultrasonic energy, grinding, or any combination thereof.
11. 11 . The method of claim 9 , further comprising removing the material after bonding the first semiconductor die and the second semiconductor die to one of a substrate, a leadframe, an additional die, a lead, a redistribution layer, or any combination thereof.
12. 12 . The method of claim 9 , wherein the material comprises two or more layers.
13. 13 . The method of claim 9 , wherein the thickness is between 0.1 microns and 125 microns.
14. 14 . The method of claim 9 , wherein temporarily coupling the material to the first semiconductor die and to the second semiconductor die occurs after the first semiconductor die and the second semiconductor die have been singulated from a substrate comprising a plurality of semiconductor die.
15. 15 . A method of reinforcing a semiconductor device comprising: one of permanently coupling or temporarily coupling a material to a first semiconductor die and to a second semiconductor die coupled together in a single semiconductor device at one of a largest planar surface, a thickness, or any combination of each of the first semiconductor die and the second semiconductor die; and reducing a warpage of the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die to less than 200 microns through the material; wherein the largest planar surface of the first semiconductor die and the largest planar surface the second semiconductor die lie in a same plane when coupled together by the material.
16. 16 . The method of claim 15 , wherein the thickness of the first semiconductor die and the thickness of the second semiconductor die are each between 0.1 microns and 125 microns.
17. 17 . The method of claim 15 , wherein the material is a mold compound.
18. 18 . The method of claim 15 , further comprising removing the material from the first semiconductor die and from the second semiconductor die using one of light, etching, peeling, ultrasonic energy, grinding, or any combination thereof.
19. 19 . The method of claim 15 , wherein the material comprises two or more layers.
20. 20 . The method of claim 15 , further comprising removing the material after bonding the first semiconductor die and the second semiconductor die to one of a substrate, a leadframe, an additional die, a lead, a redistribution layer, or any combination thereof.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a divisional application of the earlier U.S. Utility patent application to Carney et al., entitled “Multichip Module Supports and Related Methods,” application Ser. No. 16/862,152, filed Apr. 29, 2020, now pending, the disclosure of which is hereby incorporated entirely herein by reference. BACKGROUND 1. Technical Field Aspects of this document relate generally to semiconductor packages, such as wafer scale or chip scale packages. More specific implementations involve packages including an encapsulating or mold compound. 2. Background Semiconductor packages work to facilitate electrical and physical connections to an electrical die or electrical component in the package. A protective cover or molding has generally covered portions of the semiconductor packages to protect the electrical die or electrical component from, among other things, the environment, electrostatic discharge, and electrical surges. SUMMARY Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns. Implementations of semiconductor devices may include one, all, or any of the following: The thickness may be between 0.1 microns and 125 microns. The perimeter of at least two semiconductor die rectangular and a size of the at least two semiconductor die may be at least 6 mm by 6 mm. The perimeter of the at least two semiconductor die may be rectangular and a size of the at least two semiconductor die may be 211 mm by 211 mm or smaller. The permanent die support structure may include a mold compound. The perimeter of the at least two semiconductor die may include a closed shape. The one of the permanent die support structure, the temporary die support structure, or any combination thereof may include a perimeter including a closed shape. The device may include a second permanent die support structure, a second temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The permanent die support structure, the temporary die support structure, or any combination thereof may include two or more layers. Implementations of a die support structure may include a material configured to be one of permanently coupled or temporarily coupled with a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface where the material may be configured to be coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The thickness may be between 0.1 microns and 125 microns. Implementations of die support structures may include one, all, or any of the following: The material may be configured to reduce a warpage of one of the first largest planar surface or the second largest planar surface to less than 200 microns. The material may be a mold compound. The material may be configured to be removable by one of exposure to light, ultrasonic energy, peeling, etching, grinding, or any combination thereof. The material may include a perimeter including a closed shape. The material may be a first portion of material and may include a second portion of material configured to be coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. Implementations of a method of forming a die support structure may include one of permanently coupling or temporarily coupling a material with a first largest planar surface, a second largest planar surface, a thickness between the first largest planar surface and the second largest planar surface, or any combination thereof. The first largest planar surface, a second largest planar surface, and the thickness may be formed by at least two or more semiconductor die. Implementations may include reducing a warpage of one of the first largest planar surface or the second largest planar surface to less than 200 microns through the material. Implementations of a method of forming a die support structure may include one, all, or any of the following: T