US-12622314-B2 - Dam structure for integrated passive device integration and methods of forming the same

US12622314B2US 12622314 B2US12622314 B2US 12622314B2US-12622314-B2

Abstract

An embodiment semiconductor package assembly may include an interposer, an integrated passive device electrically coupled to a first side of the interposer, an underfill material portion formed between the integrated passive device and the first side of the interposer, and a dam protruding from the first side of the interposer and configured to constrain a spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer that also includes a component of a redistribution interconnect structure. The dam may further be electrically isolated from the redistribution interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.

Inventors

Hsien-Wei Chen
Meng-Liang Lin
Shin-puu Jeng

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date: 20260505
Application Date: 20220412

Claims (20)

1 . A method of forming a semiconductor package assembly, comprising: forming an interposer by performing operations comprising: forming a first dielectric layer on a carrier substrate; forming a dam and a first portion of a redistribution interconnect structure in the first dielectric layer, wherein the dam comprises at least one tapered sidewall; forming one or more additional dielectric layers and one or more respective additional portions of the redistribution interconnect structure; dispensing an underfill material portion such that the underfill material portion, wherein the dam is configured to constrain a spatial extent of the underfill material portion removing the carrier substrate to reveal a first side of the interposer comprising a package side dielectric layer; and removing a portion of the package side dielectric layer to expose a first portion of the at least one tapered sidewall such that the dam comprises the first portion extending above the first side of the interposer and a second portion of the tapered sidewall embedded below the first side of the interposer.
2 . The method of claim 1 , further comprising: forming a first plurality of bonding structures on the redistribution interconnect structure such that the first plurality of bonding structures are configured to protrude from the first side of the interposer; electrically connecting an integrated passive device to the first plurality of bonding structures, wherein the underfill material portion is configured to form in a volume between the integrated passive device and the first side of the interposer.
3 . The method of claim 1 , wherein forming the dam further comprises: forming a via in the first dielectric layer; and depositing a conductive material in the via to thereby form the dam.
4 . The method of claim 1 , wherein forming the dam further comprises: configuring the dam to have a shape that forms a boundary of a two-dimensional region of the first side of the interposer as viewed in a plan view, wherein the dam is configured to form one of: a connected boundary that encloses a rectangular region of the first side of the interposer as viewed in the plan view; or a disconnected boundary comprising a plurality of disconnected segments.
5 . The method of claim 1 , further comprising: forming a second plurality of bonding having tapered sidewalls structures on the redistribution interconnect structure such that the second plurality of bonding structures are configured to protrude from a second side of the interposer; and electrically bonding one or more semiconductor device dies to the second plurality of bonding structures.
6 . A method of forming a semiconductor package assembly, comprising: forming a first dielectric layer; forming a dam and a first portion of a redistribution interconnect structure in the first dielectric layer; etching back a portion of the first dielectric layer to expose a top portion of the dam, wherein the top portion of the dam includes a tapered sidewall such that a width of the dam linearly decreases in a vertical direction from the top portion of the dam towards the dielectric layer; electrically connecting an integrated passive device to a first plurality of bonding structures located on the redistribution interconnect structure; and dispensing an underfill material portion such that the underfill material portion is configured to form in a volume between the integrated passive device and the first side of the interposer, wherein the top portion of the dam surrounds a perimeter of the underfill material and is configured to constrain a spatial extent of the underfill material portion.
7 . The method of claim 6 , further comprising: forming one or more additional dielectric layers and one or more respective additional portions of the redistribution interconnect structure; exposing a package side dielectric layer; and removing a portion of the package side dielectric layer to expose a first portion of the dam.
8 . The method of claim 6 , wherein forming the dam further comprises: forming a via in the first dielectric layer, wherein a bottom width of the via is larger than a top width of the via; and depositing a conductive material in the via to thereby form the dam.
9 . The method of claim 6 , wherein forming the dam further comprises: configuring the dam to have a shape that forms a boundary of a two-dimensional region of the first side of the interposer as viewed in a plan view.
10 . The method of claim 9 , wherein the dam is configured to form a continuous connected boundary that encloses a rectangular region of the first side of the interposer as viewed in the plan view such that the continuous connected boundary fully encloses the underfill material portion.
11 . The method of claim 9 , wherein the dam is configured to form a disconnected boundary comprising a plurality of disconnected segments.
12 . The method of claim 6 , further comprising: forming a second plurality of bonding structures having tapered sidewalls on the redistribution interconnect structure such that the second plurality of bonding structures configured to protrude from a second side of the interposer; and electrically bonding one or more semiconductor device dies to the second plurality of bonding structures.
13 . The method of claim 7 , wherein revealing the package side dielectric layer further comprises removing a carrier substrate to reveal a first side of an interposer.
14 . The method of claim 7 , wherein removing a portion of the package side dielectric layer further comprises exposing a first portion of the dam such that the dam comprises the first portion extending above the first side of an interposer having a first height and a second portion formed below the first side of the interposer having a second height, such that a ratio of the first height to the second height is between about 0.1 to about 0.5.
15 . A method of forming a semiconductor package assembly, comprising: forming an interposer by performing operations comprising: forming a first dielectric layer on a carrier substrate; forming a dam structure having a tapered sidewall and a first portion of a redistribution interconnect structure in the first dielectric layer; forming one or more additional dielectric layers and one or more respective additional portions of the redistribution interconnect structure; removing the carrier substrate to expose a first side of the interposer comprising a package side dielectric layer; and removing a portion of the package side dielectric layer to expose a first portion of the dam such that the dam comprises the first portion extending above the first side of the interposer including a first tapered sidewall portion and a second portion embedded below the first side of the interposer including a second tapered sidewall portion, wherein the first tapered sidewall portion is tapered at a same angle as the second tapered sidewall portion; electrically connecting an integrated passive device to a first plurality of bonding structures on the redistribution interconnect structure; and dispensing an underfill material portion that is configured to form in a volume between the integrated passive device and the first side of the interposer and surrounded by the dam structure.
16 . The method of claim 15 , wherein forming the dam structure further comprises: forming a via in the first dielectric layer, wherein a bottom width of the via is larger than a top width of the via; and depositing a conductive material in the via to thereby form the dam structure, wherein the dam structure is electrically isolated from the redistribution interconnect structure.
17 . The method of claim 15 , wherein forming the dam structure further comprises configuring the dams to have a shape that forms a boundary of a two-dimensional region of the first side of the interposer as viewed in a plan view.
18 . The method of claim 17 , wherein the dam structure is configured to form a connected boundary that encloses a rectangular region of the first side of the interposer as viewed in the plan view.
19 . The method of claim 17 , wherein the dam structure is configured to form a disconnected boundary comprising a plurality of disconnected segments.
20 . The method of claim 15 , further comprising: forming a second plurality of bonding structures having tapered sidewalls on the redistribution interconnect structure such that the second plurality of bonding structures are configured to protrude from a second side of the interposer; and electrically bonding one or more semiconductor device dies to the second plurality of bonding structures.

Description

BACKGROUND The semiconductor industry has grown due to continuous improvements in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. In addition to smaller electronic components, improvements to the packaging of components have been developed in an effort to provide smaller packages that occupy less area than previous packages. Such packaging improvements may include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), package on package (PoP), System on Chip (SoC) or System on Integrated Circuit (SoIC) devices. Some of these three-dimensional devices (e.g., 3DIC, SoC, SoIC) are prepared by placing chips over chips on a semiconductor wafer level. These three-dimensional devices provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to three-dimensional devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is top view of a semiconductor device, according to various embodiments. FIG. 1B is a vertical cross-sectional view of a semiconductor device, according to various embodiments. FIG. 1C is a vertical cross-sectional view of a further semiconductor device, according to various embodiments. FIG. 2A is a vertical cross-sectional view of an exemplary semiconductor package assembly having a fan-out wafer-level package including a plurality of semiconductor dies and an integrated passive device die, according to various embodiments. FIG. 2B is a bottom view of a portion of the exemplary semiconductor package assembly of FIG. 2A such that the plane of the figure is parallel to the cross sectional plane B-B′ shown in FIG. 2A, according to various embodiments. FIG. 3A is a vertical cross-sectional view of an exemplary semiconductor package assembly having a fan-out wafer-level package including a plurality of semiconductor dies, an integrated passive device, and a dam, according to various embodiments. FIG. 3B is a bottom view of a portion of the exemplary semiconductor package assembly of FIG. 3A such that the plane of the figure is parallel to the cross-sectional plane B-B′ shown in FIG. 3A, according to various embodiments. FIG. 3C is a vertical cross-sectional view of a portion of the interposer of FIGS. 3A and 3B, defined by the cross-section C-C′ indicated in FIG. 3B, according to various embodiments. FIG. 3D is an enlarged view of a portion of the dam shown in FIGS. 3A to 3C, according to various embodiments. FIG. 3E is a bottom view of a portion of an exemplary semiconductor package assembly similar to that of FIG. 3A showing a dam having a plurality of disconnected segments, according to various embodiments. FIG. 3F is a bottom view of a portion of an exemplary semiconductor package assembly similar to that of FIG. 3A showing a further dam having a plurality of disconnected segments, according to various embodiments. FIG. 4 is a vertical cross-sectional view of an intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 5 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 6 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 7 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 8 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 9 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 10 is a vertical cross-sectional view of a further intermediate structure that may be used in the formation of a semiconductor package assembly, according to various embodiments. FIG. 11 is a vertical cross-sectional view of a semiconductor package assembly,