US-12622316-B2 - Semiconductor structure of cell array formed by cells with hybrid cell heights

Abstract

Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a plurality of first cells arranged in a first column, a plurality of second cells arranged in a second column abutting the first column and a third cell arranged in the first column. Each first cell has a first cell height and is configured to perform a first function. Each second cell has a second cell height and is configured to perform a second function. The third cell has a third cell height and is configured to perform a third function. Each second cell is coupled to and in contact with a respective first cell. The second cell height is greater than the first cell height, and the number of first cells is equal to the number of second cells. The third cell height is proportional to the first cell height.

Inventors

• Wen-Cheng Wang
• Yung-Chieh Yu

Assignees

• MEDIATEK INC.

Dates

Publication Date

20260505

Application Date

20211028

Claims (20)

1. 1 . A semiconductor structure, comprising: a cell array, comprising: a plurality of first cells arranged in a first column, each having a first cell height along a first direction and configured to perform a first function; a plurality of second cells arranged in a second column abutting the first column, each having a second cell height along the first direction and configured to perform a second function; and at least one third cell arranged in the first column, having a third cell height along the first direction and configured to perform a third function that is different from the first function and the second function, wherein along the first direction, a first side of the third cell is abutting a side of one of two of the first cells adjacent to each other, a second side of the third cell is abutting a side of the other of the two of the first cells adjacent to each other, and the second side of the third cell is opposite to the first side of the third cell; wherein each of the second cells is coupled to and directly in contact with a respective first cell, and configured to receive at least one signal from the respective first cell and provide an output signal according to the received signal, wherein the second cell height is greater than the first cell height, and the number of the first cells is equal to that of the second cells, wherein the third cell height is half of the first cell height.
2. 2 . The semiconductor structure as claimed in claim 1 , wherein each of the first and second cells comprises: a power line extending along a second direction wherein the second direction is perpendicular to the first direction, and the first direction is parallel to the first column and the second column; a ground line extending along the second direction; a plurality of transistors disposed between the power line and the ground line and configured to perform the first or second function; and a plurality of metal lines extending along the second direction and over the transistors.
3. 3 . The semiconductor structure as claimed in claim 2 , wherein the power lines and the ground lines in the first and second cells have the same width.
4. 4 . The semiconductor structure as claimed in claim 2 , wherein the metal lines in the first cells are narrower than the metal lines in the second cells.
5. 5 . The semiconductor structure as claimed in claim 1 , wherein the third cell is a dummy cell or a guard ring cell.
6. 6 . The semiconductor structure as claimed in claim 1 , wherein each of the first cells comprises a plurality of device units and a routing unit arranged in the same row, wherein the device units are configured to perform the first function so as to generate the signal, and the routing unit comprises at least one interconnect structure that is configured to transmit the signal to the second cell.
7. 7 . The semiconductor structure as claimed in claim 6 , wherein in the first column, the interconnect structures of the routing units of two adjacent first cells are different.
8. 8 . The semiconductor structure as claimed in claim 6 , wherein a unit width of the device unit is greater than a unit width of the routing unit.
9. 9 . A semiconductor structure, comprising: a cell array, comprising: a plurality of first cells arranged in a first column, each having a first cell height along a first direction and configured to perform a first function; a plurality of second cells arranged in a second column abutting the first column, each having a second cell height along the first direction and configured to perform a second function; at least one third cell arranged in the first column, having a third cell height along the first direction and configured to perform a third function that is different from the first function, wherein along the first direction, a first side of the third cell is abutting a side of one of two of the first cells adjacent to each other, a second side of the third cell is abutting a side of the other of the two of the first cells adjacent to each other, and the second side of the third cell is opposite to the first side of the third cell; and at least one fourth cell arranged in the second column, having half of the second cell height along the first direction and configured to perform a fourth function that is different from the second function, wherein along the first direction, a first side of the fourth cell is abutting a side of one of two of the second cells adjacent to each other, a second side of the fourth cell is abutting a side of the other of the two of the second cells adjacent to each other, and the second side of the fourth cell is opposite to the first side of the fourth cell, wherein each of the first cells is coupled to and directly in contact with a respective second cell, and configured to provide at least one signal to the respective second cell according to an input signal, wherein the second cell height is greater than the first cell height, and the number of the first cells is equal to that of the second cells, wherein the third cell height is half of the first cell height.
10. 10 . The semiconductor structure as claimed in claim 9 , wherein each of the first and second cells comprises: a first power line extending along a second direction that is perpendicular to the first direction; a second power line extending along the second direction; a third power line extending along the second direction and disposed between the first and second power lines; a plurality of transistors disposed between the first and third power lines and between the second and third power lines and configured to perform the first or second function; and a plurality of metal lines extending along the second direction and over the transistors, wherein when a power voltage is applied to the first and second power lines, the third power line is grounded, and when the power supply is applied to the third power line, the first and second power lines are grounded.
11. 11 . The semiconductor structure as claimed in claim 10 , wherein the first, second and third power lines in the first and second cells have the same width.
12. 12 . The semiconductor structure as claimed in claim 10 , wherein the metal lines in the first cells are narrower than the metal lines in the second cells.
13. 13 . The semiconductor structure as claimed in claim 9 , wherein each of the third and fourth cells is a dummy cell or a guard ring cell.
14. 14 . The semiconductor structure as claimed in claim 9 , wherein each of the first cells comprises a plurality of device units and a routing unit arranged in the same row, wherein the device units are configured to perform the first function so as to generate the signal, and the routing unit comprises at least one interconnect structure that is configured to transmit the signal to the second cell.
15. 15 . The semiconductor structure as claimed in claim 9 , wherein the third cell is disposed in the middle of the first column and the fourth cell is disposed in the middle of the second column, wherein the third cell of the first column abuts the fourth cell in the second column.
16. 16 . A method for providing a cell array, comprising: obtaining a first cell height of a plurality of first cells and a second cell height of a plurality of second cells along a first direction, wherein the second cell height is greater than the first cell height; obtaining an array height of the cell array according to a least common multiple of the first cell height and the second cell height; arranging the second cells in a first column of the cell array; arranging the first cells in a second column of the cell array, wherein the number of first cells arranged in the second column is equal to the number of second cells arranged in the first column, and each of the second cells is coupled to and directly in contact with a respective first cell; and arranging at least one first additional cell having a third cell height along the first direction in the second column of the cell array, wherein along the first direction, a first side of the first additional cell is abutting a side of one of two of the first cells adjacent to each other a second side of the first additional cell is abutting a side of the other of the two of the first cells adjacent to each other, and the second side of the first additional cell is opposite to the first side of the first additional cell, wherein each of the first cells is configured to perform a first function and each of the second cells is configured to perform a second function that is different from the first function, wherein the third cell height is half of the first cell height, wherein each of the first cells comprises an interconnect structure configured to couple to and in contact with a respective second cell.
17. 17 . The method as claimed in claim 16 , wherein the first additional cell is a dummy cell or a guard ring cell.
18. 18 . The method as claimed in claim 16 , wherein in the second column, the interconnect structures of two adjacent first cells are different.
19. 19 . The method as claimed in claim 16 , wherein each of the first and second cells comprises: a power line; a ground line parallel to the power line; a plurality of transistors disposed between the power line and the ground line and configured to perform the first or second function; and a plurality of metal lines parallel to the power line and over the transistors.
20. 20 . The method as claimed in claim 19 , wherein the power lines and the ground lines in the first and second cells have the same width, and the metal lines in the first cells are narrower than the metal lines in the second cells.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This Application claims priority of U.S. Provisional Application No. 63/116,937, filed on Nov. 23, 2020, and U.S. Provisional Application No. 63/213,308, filed on Jun. 22, 2021, the entirety of which are incorporated by reference herein. BACKGROUND OF THE INVENTION Field of the Invention The invention relates to a cell array, and more particularly to a cell array formed by cells with hybrid cell heights. Description of the Related Art Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include cell phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly include powerful and efficient on-board data storage and logic circuitry for signal control and processing. With the increasing down-scaling of integrated circuits, the integrated circuits become more compact. For various cells that are frequently used in integrated circuits, when the cell height difference increases, the arrangement of the cells becomes more complicated. Therefore, a cell array with hybrid cell height is desired. BRIEF SUMMARY OF THE INVENTION Semiconductor structures are provided. An embodiment of a semiconductor structure is provided. The semiconductor structure includes a cell array. The cell array includes a plurality of first cells arranged in a first column, a plurality of second cells arranged in a second column abutting the first column, and at least one third cell arranged in the first column. Each of the first cells has a first cell height along a first direction and is configured to perform a first function. Each of the second cells has a second cell height along the first direction and is configured to perform a second function. The third cell has a third cell height along the first direction and is configured to perform a third function that is different from the first function and the second function. Each of the second cells is coupled to and in contact with a respective first cell, and configured to receive at least one signal from the respective first cell and provide an output signal according to the received signal. The second cell height is greater than the first cell height, and the number of first cells is equal to the number of second cells. The third cell height is proportional to the first cell height. Furthermore, an embodiment of a semiconductor structure is provided. The semiconductor structure includes a cell array. The cell array includes a plurality of first cells arranged in a first column, a plurality of second cells arranged in a second column abutting the first column, at least one third cell arranged in the first column, and at least one fourth cell arranged in the second column. Each of the first cells has a first cell height along a first direction and is configured to perform a first function. Each of the second cells has a second cell height along the first direction and is configured to perform a second function. The third cell has a third cell height along the first direction and is configured to perform a third function that is different from the first function. The fourth cell has half of the second cell height along the first direction and is configured to perform a fourth function that is different from the second function. Each of the first cells is coupled to and in contact with a respective second cell, and configured to provide at least one signal to the respective second cell according to an input signal. The second cell height is greater than the first cell height, and the number of first cells is equal to the number of second cells. The third cell height is proportional to the first cell height. Moreover, an embodiment of a method for providing a cell array is provided. The first cell height of a plurality of first cells and the second cell height of a plurality of second cells are obtained. The second cell height is greater than the first cell height. The array height of the cell array is obtained according to a least common multiple of the first cell height and the second cell height. The second cells are arranged in a first column of the cell array. The first cells are arranged in a second column of the cell array. The number of first cells arranged in the second column is equal to the number of second cells arranged in the first column, and each of the second cells is coupled to and in contact with a respective first cell. At least one first additional cell having a third cell height is arranged in the second column of the cell array. Each of the first cells is configured to perform a first function and each of the second cells is configured to perform a second function that is different from the first function. The third cell height is proportional to the first cell height. Each of the first cells comprises an interconnect structur