US-12622317-B2 - Packaging architecture for modular die interoperability

Abstract

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

Inventors

• Adel A. Elsherbini
• Stephen R. Van Doren
• Ritu Gupta
• Gerald S. Pasdast
• Robert J. Munoz
• Shawna M. Liff

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20211221

Claims (20)

1. 1 . A microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer, wherein: a first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises a repeater circuitry in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality, wherein the repeater circuitry comprises an amplifier, and the second IC die is part of an array of bridge dies having smaller sizes than the surrounding IC dies in the first plurality.
2. 2 . The microelectronic assembly of claim 1 , wherein: the first IC die is larger than the surrounding IC dies, and the second IC die is at least one of longer and wider than adjacent IC dies in the second plurality.
3. 3 . The microelectronic assembly of claim 1 , wherein: the second plurality of IC dies is embedded in a dielectric in the second layer, and through-dielectric vias (TDVs) in the second layer provide electrical coupling between the first layer and a third layer.
4. 4 . The microelectronic assembly of claim 1 , further comprising a redistribution layer (RDL) between the second layer and a package substrate.
5. 5 . The microelectronic assembly of claim 1 , further comprising a third IC die in the first layer coupled mechanically to the second IC die, wherein the third IC die does not comprise any functional electrical circuits.
6. 6 . The microelectronic assembly of claim 1 , wherein: a third IC die in the first plurality of IC dies has an incompatible communication interface with adjacent IC dies in the first plurality, and a fourth IC die in the second plurality of IC dies comprises a circuit for protocol translation that enables the third IC die to communicate with the adjacent IC dies.
7. 7 . The microelectronic assembly of claim 1 , further comprising other IC dies in the first layer that are not part of the first plurality.
8. 8 . An IC package comprising: a first IC die in a first layer; a second IC die in a second layer between the first layer and a third layer; and a package substrate in the third layer, wherein: the first IC die is part of an array of uniformly sized IC dies in the first layer, the first IC die is differently sized than the uniformly sized IC dies, the second IC die is part of another array of bridge dies having smaller sizes than the array of uniformly sized IC dies; and the second IC die comprises a repeater circuitry in an electrical pathway coupling the first IC die with an adjacent IC die in the array of uniformly sized IC dies, the repeater circuitry comprising an amplifier.
9. 9 . The IC package of claim 8 , wherein a RDL between the second layer and the third layer accommodates electrical routing for the differently sized first IC die.
10. 10 . The IC package of claim 8 , wherein: the first IC die has a first interface for communication with an adjacent IC die, the adjacent IC die has a second interface for communication with the first IC die, the first interface and the second interface are incompatible, such that the first IC die cannot communicate with the adjacent IC die, and the second IC die comprises a circuit for protocol translation between the first interface and the second interface, such that the first IC die is enabled to communicate with the adjacent IC die through the circuit.
11. 11 . The IC package of claim 8 , wherein the second layer comprises a dielectric with TDVs surrounding the second IC die.
12. 12 . The IC package of claim 11 , wherein the dielectric comprises inorganic material.
13. 13 . The IC package of claim 8 , wherein the package substrate comprises one of a silicon interposer and an organic substrate.
14. 14 . A server architecture comprising: an array of core complexes in individual IC dies in a first layer, electrically coupled along edges of the individual IC dies by bridge dies in a second layer not coplanar with the first layer, wherein: the array forms a modular tiled compute architecture, at least one IC die has a different footprint than other IC dies in the first layer and a different routing from the other IC dies in the first layer, wherein an RDL between the second layer and a package substrate accommodates the different routing, and at least one bridge die electrically coupled to the at least one IC die comprises a repeater circuitry in an electrical pathway coupling the at least one IC die with an adjacent IC die in the first layer, the repeater circuitry configured to amplify a signal in the electrical pathway.
15. 15 . The server architecture of claim 14 , wherein: the at least one bridge die comprises the repeater circuitry, and the at least one bridge die is larger than adjacent bridge dies in the second layer.
16. 16 . The server architecture of claim 14 , wherein: one of the core complexes is in another IC die that has an incompatible communication interface with other adjacent IC dies, and another one of the bridge dies electrically coupled to the another IC die comprises circuitry for protocol translation that enables the another IC die to communicate with the other adjacent IC dies.
17. 17 . The IC package of claim 8 , wherein the first IC die is larger than the uniformly sized IC dies.
18. 18 . The server architecture of claim 14 , wherein the at least one IC die has a larger footprint than the other IC dies in the first layer.
19. 19 . The server architecture of claim 14 , wherein the at least one bridge die in the second layer has a smaller footprint than the individual IC dies in the first layer.
20. 20 . The IC package of claim 8 , wherein the first IC die has different routing from the uniformly sized IC dies.

Description

TECHNICAL FIELD The present disclosure relates to techniques, methods, and apparatus directed to packaging architecture for modular die interoperability in semiconductor integrated circuit (IC) packaging. BACKGROUND Electronic circuits when commonly fabricated on a wafer of semiconductor material, such as silicon, are called ICs. The wafer with such ICs is typically cut into numerous individual dies. The dies may be packaged into an IC package containing one or more dies along with other electronic components such as resistors, capacitors, and inductors. The IC package may be integrated onto an electronic system, such as a consumer electronic system, or servers, such as mainframes. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIG. 1 is a simplified top view of an example microelectronic assembly, according to some embodiments of the present disclosure. FIG. 2A is a simplified top view of another example microelectronic assembly, according to various embodiments of the present disclosure. FIG. 2B is a simplified cross-sectional view of the example microelectronic assembly of FIG. 2A. FIG. 3A is a simplified top view of yet another example microelectronic assembly, according to various embodiments of the present disclosure. FIGS. 3B-3C are schematic block diagrams of details associated with the example microelectronic assembly of FIG. 3A. FIGS. 4A-4C are simplified cross-sectional views of example microelectronic assemblies, according to various embodiments. FIG. 5 is a simplified top view of yet another example microelectronic assembly, according to various embodiments of the present disclosure. FIG. 6 is a simplified cross-sectional view of yet another example microelectronic assembly, according to various embodiments of the present disclosure. FIG. 7 is a cross-sectional view of a device package that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 8 is a cross-sectional side view of a device assembly that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. FIG. 9 is a block diagram of an example computing device that includes one or more microelectronic assemblies in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION Overview For purposes of illustrating IC packages described herein, it is important to understand phenomena that may come into play during assembly and packaging of ICs. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. Advances in semiconductor processing and logic design have permitted an increase in the amount of logic circuits that may be included in processors and other IC devices. As a result, many processors now have multiple cores that are monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar since they take the form of a flat surface and are typically built on a single silicon wafer made from a monocrystalline silicon boule. The typical manufacturing process for such monolithic ICs is called a planar process, allowing photolithography, etching, heat diffusion, oxidation, and other such processes to occur on the surface of the wafer, such that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer. Current technologies permit hundreds and thousands of such active circuit elements to be formed on a single die so that numerous logic circuits may be enabled thereon. In such monolithic dies, the manufacturing process must be optimized for all the circuits equally, resulting in trade-offs between different circuits. In addition, because of the limitation of having to place circuits on a planar surface, some circuits are farther apart from some others, resulting in decreased performance such as longer delays. The manufacturing yield may also be severely impacted because the entire die may have to be discarded if even one circuit is malfunctional. One solution to overcome such negative impacts of monolithic dies is to disaggregate the circuits into smaller dies (e.g., chiplets, tiles) electrically coupled by interconnect bridges. The smaller dies are part of an assembly of interconnected dies that together form a complete IC in terms of application and/or functionality, such as a memory chip, microprocessor, microcontroller, commodity IC (e.g., chip