US-12622318-B2 - Wafer to wafer high density interconnects

Abstract

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

Inventors

• Timothy J. Chainer
• Mark D. Schultz
• Russell A. Budd
• Todd Edward Takken
• Matthew Doyle

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20211228

Claims (20)

1. 1 . A wafer scale system, comprising: a plurality of wafers mounted on a substrate, wherein the plurality of wafers comprises a first wafer and a second wafer, the first wafer is adjacent to the second wafer, and each of the first wafer and the second wafer comprises a plurality of die sites; and a high density interconnect structure that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connects one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer.
2. 2 . The wafer scale system of claim 1 , wherein the high density interconnect structure is a silicon bridge.
3. 3 . The wafer scale system of claim 2 , wherein two or more wafers of the plurality of wafers are mounted on a shared substrate.
4. 4 . The wafer scale system of claim 3 , wherein a coefficient of thermal expansion (CTE) of the two or more wafers is matched to a CTE of the substrate.
5. 5 . The wafer scale system of claim 2 , wherein the silicon bridge includes two or more silicon bridges to connect the one or more die sites of the plurality of die sites of the first wafer to the one or more die sites of the plurality of die sites of the second wafer.
6. 6 . The wafer scale system of claim 2 , wherein the silicon bridge provides a signal line pitch of less than about 1 micron.
7. 7 . The wafer scale system of claim 1 , wherein the high density interconnect structure is a thinned silicon bridge, and the thinned silicon bridge provides a flexible interconnection between the one or more die sites of the plurality of die sites of the first wafer to the one or more die sites of the plurality of die sites of the second wafer.
8. 8 . The wafer scale system of claim 7 , wherein each wafer of the plurality of wafers is independently mounted on a distinct and separate substrate.
9. 9 . The wafer scale system of claim 7 , wherein the thinned silicon bridge provides a signal line pitch of less than 1 micron.
10. 10 . The wafer scale system of claim 1 , wherein: each wafer of the plurality of wafers is disposed in a respective wafer pod of a plurality of wafer pods, a first wafer pod, of the plurality of wafer pods, includes a multilayer flex structure that terminates in a first connector of a plurality of connectors, the first wafer pod is adjacent to a second wafer pod of the plurality of wafer pods, the first connector is adjacent to a second connector of the plurality of connectors, and the first connector is configured to connect with the second connector of the second wafer pod.
11. 11 . The wafer scale system of claim 10 , wherein; two or more multilayer flex structures connect the first wafer pod with the second wafer pod, and the two or more multilayer flex structures include the multilayer flex structure.
12. 12 . The wafer scale system of claim 10 , wherein each multilayer flex structure of two or more multilayer flex structures provides a signal line pitch of less than 10 microns.
13. 13 . The wafer scale system of claim 1 , further comprising a cooling structure disposed between each wafer of the plurality of wafers and the substrate.
14. 14 . The wafer scale system of claim 1 , wherein; a frontside of one or more wafers of the plurality of wafers has through silicon vias, and the one or more wafers are mounted onto the substrate.
15. 15 . The wafer scale system of claim 14 , where a backside of the one or more wafers of the plurality of wafers includes redistribution layers to connect to the high density interconnect structure.
16. 16 . A wafer scale system, comprising: two or more wafers mounted on a substrate, wherein the two or more wafers comprise a first wafer and a second wafer, the first wafer is adjacent to the second wafer, and each of the first wafer and the second wafer comprises a plurality of die sites; and a silicon bridge that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connect one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer, wherein the silicon bridge provides a signal line pitch of less than 1 micron.
17. 17 . The wafer scale system of claim 16 , wherein: the two or more wafers are mounted on a shared substrate, and a coefficient of thermal expansion (CTE) of the two or more wafers is matched to a CTE of the shared substrate.
18. 18 . The wafer scale system of claim 16 , wherein: the silicon bridge is a thinned silicon bridge, the thinned silicon bridge provides a flexible interconnection between the one or more die sites of the plurality of die sites of the first wafer and the one or more die sites of the plurality of die sites of the second wafer, and each wafer of the two or more wafers is independently mounted on a distinct and separate substrate.
19. 19 . A wafer scale system, comprising: two or more wafers each packaged in a first wafer pod of a plurality of wafer pods, wherein the two or more wafers comprise a first wafer and a second wafer, the first wafer is adjacent to the second wafer, and each of the first wafer and the second wafer comprises a plurality of die sites; a silicon bridge that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connect one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer; and a multilayer flex structure connected to each wafer of the two or more wafers, wherein the multilayer flex structure terminates in a first connector of a plurality of connectors, wherein the first wafer pod is adjacent to a second wafer pod of the plurality of wafer pods, the first connector is adjacent to a second connector of the plurality of connectors, the first connector is configured to connect with the second connector of the second wafer pod, and the multilayer flex structure provides a signal line pitch of less than 10 micron.
20. 20 . The wafer scale system of claim 19 , wherein: each wafer pod, of the plurality of wafer pods, includes one or more connectors of the plurality of connectors at each face, the one or more connectors connect the first wafer pod to four wafer pods of the plurality of wafer pods, and each wafer pod of the four wafer pods is adjacent to the first wafer pod.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This application was made with government support under contract number H98230-19-C-0113 awarded by the Maryland Procurement Office. The government has certain rights to this invention. BACKGROUND Technical Field The present disclosure generally relates to semiconductor integrated circuits, and more particularly, to structures and methods for interconnecting semiconductor wafers using a silicon bridge or a multi-layer flex bridge. Description of the Related Art In the packaging of integrated circuits, there are scenarios where it may be beneficial to interconnect semiconductor wafers in a side-by-side packaging configuration. A semiconductor wafer includes multiple die sites fabricated on the frontside on the wafer including “Back End of the Line” (BEOL) wiring levels to provide external connections to the die sites. A semiconductor wafer may include redistribution layers (RDL) on either the frontside or backside of the wafer to provide additional wiring levels. A semiconductor wafer may also include through silicon vias (TSVs), which provide electrical connections between the frontside the frontside and backside of the wafer. In one configuration, semiconductor wafers can be packaged with the backside of the wafer bonded mounted onto a package substrate. The wafer may be mounted onto a microchannel cooler to remove the heat dissipated from wafer. The package substrate provides mechanical support and provide coolant connections to the microchannel cooler. SUMMARY According to various embodiments, a structure and method are provided for interconnecting wafers with a high density interconnect structure. Such a high density connection can include a silicon bridge, a thinned silicon bridge and a multi-layer flex bridge. In one embodiment, a wafer scale system includes two or more wafers each mounted on a substrate. A silicon bridge connects adjacent ones of the two or more wafers, where the silicon bridge provides a signal line pitch of less than about 1 micron. In some embodiments, the two or more wafers are mounted on a shared substrate. A coefficient of thermal expansion (CTE) of the two or more wafers can be matched to a CTE of the substrate. In some embodiments, the silicon bridge is a thinned silicon bridge providing a flexible interconnection between the adjacent ones of the two of more wafers. The wafers may be mounted on a shared substrate or may be mounted independently on distinct and separate substrates. In on embodiment, semiconductor wafers are mounted with the backside of the wafer mounted on a shared or separate substrate In one embodiment, semiconductor wafers with TSV's are mounted with the frontside of the wafer mounted on a shared or separate substrate. In one embodiment, wafers may be mounted with the frontside of at least one wafer and the backside of at least one wafer on a shared or separate substrate. According to various embodiments, a wafer scale system includes two or more wafers each packaged in a respective wafer pod. A multilayer flex structure connects to each of the two or more wafers, where the multilayer flex structure terminates in a connector. The connector is operable to connect with an adjacent connector of an adjacent wafer pod. The multilayer flex structure can provide a signal line pitch of less than about 10 micron and be comprised of more than one layer. In some embodiments, two of more multilayer flex structures connects one of the two or more wafer pods with the adjacent wafer pod. In some embodiments, each wafer pod includes one or more of the connectors at each face thereof, providing operability to connect the wafer pod to up to four adjacent wafer pods for a rectilinear arrangement or up to 6 wafer pods if the pods are hexagonal and configured in a hexagonal close packed (HCP) arrangement. By virtue of the concepts discussed herein, the structure and methods provided herein improve upon approaches currently used to interconnect wafers. These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps. FIG. 1A is a schematic representation of a frontside wafer to wafer interconnect using a silicon bridge, consistent with an illustrative embodiment. FIG. 1B is a schematic representation of a backside wafer to wafer interconnect with through silicon vias and redistributi